335 lines
11 KiB
ArmAsm
335 lines
11 KiB
ArmAsm
/* $NetBSD: vector.s,v 1.32 1996/01/07 21:29:47 mycroft Exp $ */
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/*
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* Copyright (c) 1993, 1994, 1995 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <i386/isa/icu.h>
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#include <dev/isa/isareg.h>
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#define ICU_HARDWARE_MASK
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/*
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* These macros are fairly self explanatory. If ICU_SPECIAL_MASK_MODE is
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* defined, we try to take advantage of the ICU's `special mask mode' by only
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* EOIing the interrupts on return. This avoids the requirement of masking and
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* unmasking. We can't do this without special mask mode, because the ICU
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* would also hold interrupts that it thinks are of lower priority.
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*
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* Many machines do not support special mask mode, so by default we don't try
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* to use it.
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*/
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) / 8)
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#ifdef ICU_SPECIAL_MASK_MODE
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#define ACK1(irq_num)
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#define ACK2(irq_num) \
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movb $(0x60|IRQ_SLAVE),%al /* specific EOI for IRQ2 */ ;\
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outb %al,$IO_ICU1
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#define MASK(irq_num, icu)
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#define UNMASK(irq_num, icu) \
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movb $(0x60|(irq_num%8)),%al /* specific EOI */ ;\
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outb %al,$icu
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#else /* ICU_SPECIAL_MASK_MODE */
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#ifndef AUTO_EOI_1
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#define ACK1(irq_num) \
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movb $(0x60|(irq_num%8)),%al /* specific EOI */ ;\
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outb %al,$IO_ICU1
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#else
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#define ACK1(irq_num)
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#endif
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#ifndef AUTO_EOI_2
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#define ACK2(irq_num) \
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movb $(0x60|(irq_num%8)),%al /* specific EOI */ ;\
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outb %al,$IO_ICU2 /* do the second ICU first */ ;\
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movb $(0x60|IRQ_SLAVE),%al /* specific EOI for IRQ2 */ ;\
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outb %al,$IO_ICU1
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#else
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#define ACK2(irq_num)
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#endif
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#ifdef ICU_HARDWARE_MASK
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#define MASK(irq_num, icu) \
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movb _imen + IRQ_BYTE(irq_num),%al ;\
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orb $IRQ_BIT(irq_num),%al ;\
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movb %al,_imen + IRQ_BYTE(irq_num) ;\
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FASTER_NOP ;\
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outb %al,$(icu+1)
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#define UNMASK(irq_num, icu) \
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cli ;\
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movb _imen + IRQ_BYTE(irq_num),%al ;\
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andb $~IRQ_BIT(irq_num),%al ;\
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movb %al,_imen + IRQ_BYTE(irq_num) ;\
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FASTER_NOP ;\
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outb %al,$(icu+1) ;\
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sti
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#else /* ICU_HARDWARE_MASK */
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#define MASK(irq_num, icu)
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#define UNMASK(irq_num, icu)
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#endif /* ICU_HARDWARE_MASK */
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#endif /* ICU_SPECIAL_MASK_MODE */
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/*
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* Macros for interrupt entry, call to handler, and exit.
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*
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* XXX
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* The interrupt frame is set up to look like a trap frame. This may be a
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* waste. The only handler which needs a frame is the clock handler, and it
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* only needs a few bits. Xdoreti() needs a trap frame for handling ASTs, but
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* it could easily convert the frame on demand.
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*
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* The direct costs of setting up a trap frame are two pushl's (error code and
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* trap number), an addl to get rid of these, and pushing and popping the
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* callee-saved registers %esi, %edi, %ebx, and %ebp twice.
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*
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* If the interrupt frame is made more flexible, INTR can push %eax first and
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* decide the ipending case with less overhead, e.g., by avoiding loading the
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* segment registers.
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*
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* XXX
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* Should we do a cld on every system entry to avoid the requirement for
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* scattered cld's?
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*/
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.globl _isa_strayintr
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/*
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* Fast vectors.
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*
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* Like a normal vector, but run with all interrupts off. The handler is
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* expected to be as fast as possible, and is expected to not change the
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* interrupt flag. We pass an argument in like normal vectors, but we assume
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* that a pointer to the frame is never required. There can be only one
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* handler on a fast vector.
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*
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* XXX
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* Note that we assume fast vectors don't do anything that would cause an AST
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* or softintr; if so, it will be deferred until the next clock tick (or
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* possibly sooner).
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*/
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#define FAST(irq_num, icu, ack) \
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IDTVEC(fast/**/irq_num) ;\
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pushl %eax /* save call-used registers */ ;\
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pushl %ecx ;\
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pushl %edx ;\
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pushl %ds ;\
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pushl %es ;\
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movl $GSEL(GDATA_SEL, SEL_KPL),%eax ;\
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movl %ax,%ds ;\
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movl %ax,%es ;\
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/* have to do this here because %eax is lost on call */ ;\
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movl _intrhand + (irq_num) * 4,%eax ;\
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incl IH_COUNT(%eax) ;\
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pushl IH_ARG(%eax) ;\
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call IH_FUN(%eax) ;\
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ack(irq_num) ;\
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addl $4,%esp ;\
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incl _cnt+V_INTR /* statistical info */ ;\
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popl %es ;\
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popl %ds ;\
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popl %edx ;\
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popl %ecx ;\
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popl %eax ;\
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iret
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FAST(0, IO_ICU1, ACK1)
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FAST(1, IO_ICU1, ACK1)
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FAST(2, IO_ICU1, ACK1)
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FAST(3, IO_ICU1, ACK1)
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FAST(4, IO_ICU1, ACK1)
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FAST(5, IO_ICU1, ACK1)
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FAST(6, IO_ICU1, ACK1)
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FAST(7, IO_ICU1, ACK1)
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FAST(8, IO_ICU2, ACK2)
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FAST(9, IO_ICU2, ACK2)
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FAST(10, IO_ICU2, ACK2)
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FAST(11, IO_ICU2, ACK2)
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FAST(12, IO_ICU2, ACK2)
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FAST(13, IO_ICU2, ACK2)
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FAST(14, IO_ICU2, ACK2)
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FAST(15, IO_ICU2, ACK2)
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/*
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* Normal vectors.
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*
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* We cdr down the intrhand chain, calling each handler with its appropriate
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* argument (0 meaning a pointer to the frame, for clock interrupts).
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*
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* The handler returns one of three values:
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* 0 - This interrupt wasn't for me.
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* 1 - This interrupt was for me.
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* -1 - This interrupt might have been for me, but I don't know.
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* If there are no handlers, or they all return 0, we flags it as a `stray'
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* interrupt. On a system with level-triggered interrupts, we could terminate
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* immediately when one of them returns 1; but this is a PC.
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*
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* On exit, we jump to Xdoreti(), to process soft interrupts and ASTs.
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*/
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#define INTR(irq_num, icu, ack) \
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IDTVEC(recurse/**/irq_num) ;\
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pushfl ;\
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pushl %cs ;\
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pushl %esi ;\
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cli ;\
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_Xintr/**/irq_num/**/: ;\
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pushl $0 /* dummy error code */ ;\
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pushl $T_ASTFLT /* trap # for doing ASTs */ ;\
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INTRENTRY ;\
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MAKE_FRAME ;\
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MASK(irq_num, icu) /* mask it in hardware */ ;\
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ack(irq_num) /* and allow other intrs */ ;\
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testb $IRQ_BIT(irq_num),_cpl + IRQ_BYTE(irq_num) ;\
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jnz _Xhold/**/irq_num /* currently masked; hold it */ ;\
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_Xresume/**/irq_num/**/: ;\
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movl _cpl,%eax /* cpl to restore on exit */ ;\
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pushl %eax ;\
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orl _intrmask + (irq_num) * 4,%eax ;\
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movl %eax,_cpl /* add in this intr's mask */ ;\
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sti /* safe to take intrs now */ ;\
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movl _intrhand + (irq_num) * 4,%ebx /* head of chain */ ;\
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testl %ebx,%ebx ;\
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jz _Xstray/**/irq_num /* no handlears; we're stray */ ;\
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STRAY_INITIALIZE /* nobody claimed it yet */ ;\
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7: movl IH_ARG(%ebx),%eax /* get handler arg */ ;\
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testl %eax,%eax ;\
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jnz 4f ;\
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movl %esp,%eax /* 0 means frame pointer */ ;\
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4: pushl %eax ;\
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call IH_FUN(%ebx) /* call it */ ;\
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addl $4,%esp /* toss the arg */ ;\
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STRAY_INTEGRATE /* maybe he claimed it */ ;\
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incl IH_COUNT(%ebx) /* count the intrs */ ;\
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movl IH_NEXT(%ebx),%ebx /* next handler in chain */ ;\
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testl %ebx,%ebx ;\
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jnz 7b ;\
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STRAY_TEST /* see if it's a stray */ ;\
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5: UNMASK(irq_num, icu) /* unmask it in hardware */ ;\
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jmp _Xdoreti /* lower spl and do ASTs */ ;\
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IDTVEC(stray/**/irq_num) ;\
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pushl $irq_num ;\
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call _isa_strayintr ;\
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addl $4,%esp ;\
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jmp 5b ;\
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IDTVEC(hold/**/irq_num) ;\
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orb $IRQ_BIT(irq_num),_ipending + IRQ_BYTE(irq_num) ;\
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INTRFASTEXIT
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#if defined(DEBUG) && defined(notdef)
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#define STRAY_INITIALIZE \
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xorl %esi,%esi
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#define STRAY_INTEGRATE \
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orl %eax,%esi
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#define STRAY_TEST \
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testl %esi,%esi ;\
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jz _Xstray/**/irq_num
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#else /* !DEBUG */
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#define STRAY_INITIALIZE
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#define STRAY_INTEGRATE
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#define STRAY_TEST
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#endif /* DEBUG */
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#ifdef DDB
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#define MAKE_FRAME \
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leal -8(%esp),%ebp
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#else /* !DDB */
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#define MAKE_FRAME
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#endif /* DDB */
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INTR(0, IO_ICU1, ACK1)
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INTR(1, IO_ICU1, ACK1)
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INTR(2, IO_ICU1, ACK1)
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INTR(3, IO_ICU1, ACK1)
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INTR(4, IO_ICU1, ACK1)
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INTR(5, IO_ICU1, ACK1)
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INTR(6, IO_ICU1, ACK1)
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INTR(7, IO_ICU1, ACK1)
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INTR(8, IO_ICU2, ACK2)
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INTR(9, IO_ICU2, ACK2)
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INTR(10, IO_ICU2, ACK2)
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INTR(11, IO_ICU2, ACK2)
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INTR(12, IO_ICU2, ACK2)
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INTR(13, IO_ICU2, ACK2)
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INTR(14, IO_ICU2, ACK2)
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INTR(15, IO_ICU2, ACK2)
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/*
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* These tables are used by the ISA configuration code.
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*/
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/* interrupt service routine entry points */
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IDTVEC(intr)
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.long _Xintr0, _Xintr1, _Xintr2, _Xintr3, _Xintr4, _Xintr5, _Xintr6
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.long _Xintr7, _Xintr8, _Xintr9, _Xintr10, _Xintr11, _Xintr12
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.long _Xintr13, _Xintr14, _Xintr15
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/* fast interrupt routine entry points */
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IDTVEC(fast)
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.long _Xfast0, _Xfast1, _Xfast2, _Xfast3, _Xfast4, _Xfast5, _Xfast6
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.long _Xfast7, _Xfast8, _Xfast9, _Xfast10, _Xfast11, _Xfast12
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.long _Xfast13, _Xfast14, _Xfast15
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/*
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* These tables are used by Xdoreti() and Xspllower().
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*/
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/* resume points for suspended interrupts */
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IDTVEC(resume)
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.long _Xresume0, _Xresume1, _Xresume2, _Xresume3, _Xresume4
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.long _Xresume5, _Xresume6, _Xresume7, _Xresume8, _Xresume9
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.long _Xresume10, _Xresume11, _Xresume12, _Xresume13, _Xresume14
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.long _Xresume15
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/* for soft interrupts */
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.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.long _Xsofttty, _Xsoftnet, _Xsoftclock
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/* fake interrupts to resume from splx() */
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IDTVEC(recurse)
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.long _Xrecurse0, _Xrecurse1, _Xrecurse2, _Xrecurse3, _Xrecurse4
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.long _Xrecurse5, _Xrecurse6, _Xrecurse7, _Xrecurse8, _Xrecurse9
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.long _Xrecurse10, _Xrecurse11, _Xrecurse12, _Xrecurse13, _Xrecurse14
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.long _Xrecurse15
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/* for soft interrupts */
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.long 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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.long _Xsofttty, _Xsoftnet, _Xsoftclock
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/* Some bogus data, to keep vmstat happy, for now. */
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.globl _intrnames, _eintrnames, _intrcnt, _eintrcnt
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_intrnames:
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.long 0
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_eintrnames:
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_intrcnt:
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.long 0
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_eintrcnt:
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