179 lines
5.6 KiB
C
179 lines
5.6 KiB
C
/* $NetBSD: iq80310reg.h,v 1.4 2001/12/01 02:02:46 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IQ80310REG_H_
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#define _IQ80310REG_H_
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/*
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* Memory map and register definitions for the Intel IQ80310
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* Evaluation Board.
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*/
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/*
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* The memory map of the IQ80310 looks like so:
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*
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* ------------------------------
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* On-board devices
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* Flash Bank 0
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* FE80 0000 ------------------------------
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* DRAM
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* A000 0000 ------------------------------
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* Reserved
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* 9002 0000 ------------------------------
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* ATU Outbound Transaction
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* Windows
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* 8000 0000 ------------------------------
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* ATU Outbound Direct
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* Addressing Windows
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* 0080 0000 ------------------------------
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* Flash Bank 1
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* 0000 2000 ------------------------------
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* Reserved
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* 0000 1900 ------------------------------
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* Peripheral Memory Mapped
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* Registers
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* 0000 1000 ------------------------------
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* Initialization Boot Code
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* from Flash Bank 1
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* 0000 0000 ------------------------------
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*/
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/*
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* We map the CPLD registers VA==PA, so we go ahead and cheat
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* with register access.
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*/
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#define CPLD_READ(x) *((__volatile uint8_t *)(x))
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#define CPLD_WRITE(x, v) *((__volatile uint8_t *)(x)) = (v)
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/*
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* We allocate a page table for VA 0xfe400000 (4MB) and map the i80312
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* PCI I/O space (2 * 64L) and i80312 regisers (4K) there.
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*/
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#define IQ80310_IOPXS_VBASE 0xfe400000UL
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#define IQ80310_PIOW_VBASE IQ80310_IOPXS_VBASE
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#define IQ80310_SIOW_VBASE (IQ80310_PIOW_VBASE + I80312_PCI_XLATE_IOSIZE)
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#define IQ80310_80312_VBASE (IQ80310_SIOW_VBASE + I80312_PCI_XLATE_IOSIZE)
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/*
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* The IQ80310 on-board devices are mapped VA==PA during bootstrap.
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* Conveniently, the size of the on-board register space is 1 section
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* mapping.
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*/
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#define IQ80310_OBIO_BASE 0xfe800000UL
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#define IQ80310_OBIO_SIZE 0x00100000UL /* 1MB */
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#define IQ80310_UART1 0xfe800000UL /* XR 16550 */
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#define IQ80310_UART2 0xfe810000UL /* XR 16550 */
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#define IQ80310_XINT3_STATUS 0xfe820000UL
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#define XINT3_TIMER 0 /* CPLD timer */
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#define XINT3_ETHERNET 1 /* on-board i82559 */
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#define XINT3_UART1 2 /* 16550 #1 */
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#define XINT3_UART2 3 /* 16550 #2 */
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#define XINT3_SINTD 4 /* INTD# */
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#define XINT3_BIT(x) (1U << (x))
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#define IQ80310_BOARD_REV 0xfe830000UL /* rev F and later (??) */
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#define BOARD_REV(x) (((x) & 0xf) + '@')
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#define IQ80310_CPLD_REV 0xfe840000UL
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#define CPLD_REV(x) (((x) & 0xf) + '@')
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#define IQ80310_7SEG_MSB 0xfe840000UL
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#define IQ80310_7SEG_LSB 0xfe850000UL
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/*
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* The 7-segment display looks like so:
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*
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* A
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* +-----+
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* | |
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* F | | B
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* | G |
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* +-----+
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* | |
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* E | | C
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* | D |
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* +-----+ o DP
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*
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* Setting a bit clears the corresponding segment on the
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* display.
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*/
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#define SEG_A (1 << 0)
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#define SEG_B (1 << 1)
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#define SEG_C (1 << 2)
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#define SEG_D (1 << 3)
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#define SEG_E (1 << 4)
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#define SEG_F (1 << 5)
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#define SEG_G (1 << 6)
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#define SEG_DP (1 << 7)
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#define IQ80310_XINT0_STATUS 0xfe850000UL /* rev F and later */
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#define XINT0_SINTA 0 /* INTA# */
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#define XINT0_SINTB 1 /* INTB# */
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#define XINT0_SINTC 2 /* INTC# */
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#define XINT0_BIT(x) (1U << (x))
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#define IQ80310_XINT_MASK 0xfe860000UL
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/* See XINT_STATUS bits: 0 == int enabled, 1 == int disabled */
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#define IQ80310_BACKPLANE_DET 0xfe870000UL
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#define IQ80310_TIMER_LA0 0xfe880000UL
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#define IQ80310_TIMER_LA1 0xfe890000UL
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#define IQ80310_TIMER_LA2 0xfe8a0000UL
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#define IQ80310_TIMER_LA3 0xfe8b0000UL
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#define IQ80310_TIMER_ENABLE 0xfe8c0000UL
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#define TIMER_ENABLE_EN (1U << 0) /* enable counter */
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#define TIMER_ENABLE_INTEN (1U << 1) /* enable interrupt */
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#define IQ80310_ROT_SWITCH 0xfe8d0000UL
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#define IQ80310_JTAG 0xfe8e0000UL
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#define IQ80310_BATTERY_STAT 0xfe8f0000UL
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#define BATTERY_STAT_PRES (1U << 0)
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#define BATTERY_STAT_CHRG (1U << 1)
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#define BATTERY_STAT_DISCHRG (1U << 2)
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#define BATTERY_STAT_PWRDELAY (1U << 3) /* rev F and later */
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#endif /* _IQ80310REG_H_ */
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