832 lines
22 KiB
C
832 lines
22 KiB
C
/* $NetBSD: epe.c,v 1.2 2005/01/17 02:32:29 joff Exp $ */
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/*
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* Copyright (c) 2004 Jesse Off
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: epe.c,v 1.2 2005/01/17 02:32:29 joff Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ioctl.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/malloc.h>
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#include <sys/time.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include <arm/ep93xx/epsocvar.h>
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#include <arm/ep93xx/ep93xxvar.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_types.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/in_systm.h>
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#include <netinet/in_var.h>
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#include <netinet/ip.h>
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#include <netinet/if_inarp.h>
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#endif
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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#include "bpfilter.h"
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#include <net/bpfdesc.h>
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#endif
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#include <machine/bus.h>
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#ifdef IPKDB_EP93XX
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#include <ipkdb/ipkdb.h>
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#endif
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#include <arm/ep93xx/ep93xxreg.h>
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#include <arm/ep93xx/epereg.h>
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#include <arm/ep93xx/epevar.h>
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#ifndef EPE_FAST
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#define EPE_FAST
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#endif
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#ifndef EPE_FAST
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#define EPE_READ(x) \
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bus_space_read_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x))
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#define EPE_WRITE(x, y) \
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, (EPE_ ## x), (y))
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#define CTRLPAGE_DMASYNC(x, y, z) \
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bus_dmamap_sync(sc->sc_dmat, sc->ctrlpage_dmamap, (x), (y), (z))
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#else
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#define EPE_READ(x) *(__volatile u_int32_t *) \
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(EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x))
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#define EPE_WRITE(x, y) *(__volatile u_int32_t *) \
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(EP93XX_AHB_VBASE + EP93XX_AHB_EPE + (EPE_ ## x)) = y
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#define CTRLPAGE_DMASYNC(x, y, z)
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#endif /* ! EPE_FAST */
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static int epe_match(struct device *, struct cfdata *, void *);
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static void epe_attach(struct device *, struct device *, void *);
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static void epe_init(struct epe_softc *);
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static int epe_intr(void* arg);
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static int epe_gctx(struct epe_softc *);
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static int epe_mediachange(struct ifnet *);
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static void epe_mediastatus(struct ifnet *, struct ifmediareq *);
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int epe_mii_readreg (struct device *, int, int);
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void epe_mii_writereg (struct device *, int, int, int);
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void epe_statchg (struct device *);
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void epe_tick (void *);
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static int epe_ifioctl (struct ifnet *, u_long, caddr_t);
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static void epe_ifstart (struct ifnet *);
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static void epe_ifwatchdog (struct ifnet *);
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static int epe_ifinit (struct ifnet *);
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static void epe_ifstop (struct ifnet *, int);
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static void epe_setaddr (struct ifnet *);
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CFATTACH_DECL(epe, sizeof(struct epe_softc),
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epe_match, epe_attach, NULL, NULL);
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static int
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epe_match(struct device *parent, struct cfdata *match, void *aux)
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{
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return 2;
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}
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static void
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epe_attach(struct device *parent, struct device *self, void *aux)
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{
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struct epe_softc *sc;
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struct epsoc_attach_args *sa;
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printf("\n");
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sc = (struct epe_softc*) self;
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sa = aux;
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sc->sc_iot = sa->sa_iot;
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sc->sc_intr = sa->sa_intr;
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sc->sc_dmat = sa->sa_dmat;
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if (bus_space_map(sa->sa_iot, sa->sa_addr, sa->sa_size,
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0, &sc->sc_ioh))
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panic("%s: Cannot map registers", self->dv_xname);
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ep93xx_intr_establish(sc->sc_intr, IPL_NET, epe_intr, sc);
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epe_init(sc);
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}
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static int
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epe_gctx(struct epe_softc *sc)
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{
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struct ifnet * ifp = &sc->sc_ec.ec_if;
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u_int32_t *cur, ndq = 0;
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/* Handle transmit completions */
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cur = (u_int32_t *)(EPE_READ(TXStsQCurAdd) -
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sc->ctrlpage_dsaddr + sc->ctrlpage);
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if (sc->TXStsQ_cur != cur) {
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CTRLPAGE_DMASYNC(TX_QLEN * 2 * sizeof(u_int32_t),
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TX_QLEN * sizeof(u_int32_t), BUS_DMASYNC_PREREAD);
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} else {
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return 0;
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}
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do {
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u_int32_t tbi = *sc->TXStsQ_cur & 0x7fff;
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struct mbuf *m = sc->txq[tbi].m;
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if ((*sc->TXStsQ_cur & TXStsQ_TxWE) == 0) {
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ifp->if_oerrors++;
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}
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bus_dmamap_unload(sc->sc_dmat, sc->txq[tbi].m_dmamap);
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m_freem(m);
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do {
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sc->txq[tbi].m = NULL;
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ndq++;
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tbi = (tbi + 1) % TX_QLEN;
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} while (sc->txq[tbi].m == m);
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ifp->if_opackets++;
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sc->TXStsQ_cur++;
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if (sc->TXStsQ_cur >= sc->TXStsQ + TX_QLEN) {
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sc->TXStsQ_cur = sc->TXStsQ;
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}
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} while (sc->TXStsQ_cur != cur);
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sc->TXDQ_avail += ndq;
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if (ifp->if_flags & IFF_OACTIVE) {
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ifp->if_flags &= ~IFF_OACTIVE;
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/* Disable end-of-tx-chain interrupt */
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EPE_WRITE(IntEn, IntEn_REOFIE);
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}
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return ndq;
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}
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static int
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epe_intr(void *arg)
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{
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struct epe_softc *sc = (struct epe_softc *)arg;
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struct ifnet * ifp = &sc->sc_ec.ec_if;
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u_int32_t ndq = 0, irq, *cur;
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irq = EPE_READ(IntStsC);
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begin:
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cur = (u_int32_t *)(EPE_READ(RXStsQCurAdd) -
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sc->ctrlpage_dsaddr + sc->ctrlpage);
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CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t),
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RX_QLEN * 4 * sizeof(u_int32_t),
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BUS_DMASYNC_PREREAD);
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while (sc->RXStsQ_cur != cur) {
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if ((sc->RXStsQ_cur[0] & (RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) ==
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(RXStsQ_RWE|RXStsQ_RFP|RXStsQ_EOB)) {
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u_int32_t bi = (sc->RXStsQ_cur[1] >> 16) & 0x7fff;
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u_int32_t fl = sc->RXStsQ_cur[1] & 0xffff;
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struct mbuf *m;
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MGETHDR(m, M_DONTWAIT, MT_DATA);
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if (m != NULL) MCLGET(m, M_DONTWAIT);
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if (m != NULL && (m->m_flags & M_EXT)) {
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bus_dmamap_unload(sc->sc_dmat,
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sc->rxq[bi].m_dmamap);
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sc->rxq[bi].m->m_pkthdr.rcvif = ifp;
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sc->rxq[bi].m->m_pkthdr.len =
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sc->rxq[bi].m->m_len = fl;
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#if NBPFILTER > 0
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if (ifp->if_bpf)
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bpf_mtap(ifp->if_bpf, sc->rxq[bi].m);
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#endif /* NBPFILTER > 0 */
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(*ifp->if_input)(ifp, sc->rxq[bi].m);
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sc->rxq[bi].m = m;
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bus_dmamap_load(sc->sc_dmat,
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sc->rxq[bi].m_dmamap,
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m->m_ext.ext_buf, MCLBYTES,
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NULL, BUS_DMA_NOWAIT);
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sc->RXDQ[bi * 2] =
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sc->rxq[bi].m_dmamap->dm_segs[0].ds_addr;
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} else {
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/* Drop packets until we can get replacement
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* empty mbufs for the RXDQ.
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*/
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if (m != NULL) {
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m_freem(m);
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}
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ifp->if_ierrors++;
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}
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} else {
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ifp->if_ierrors++;
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}
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ndq++;
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sc->RXStsQ_cur += 2;
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if (sc->RXStsQ_cur >= sc->RXStsQ + (RX_QLEN * 2)) {
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sc->RXStsQ_cur = sc->RXStsQ;
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}
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}
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if (ndq > 0) {
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ifp->if_ipackets += ndq;
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CTRLPAGE_DMASYNC(TX_QLEN * 3 * sizeof(u_int32_t),
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RX_QLEN * 4 * sizeof(u_int32_t),
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BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
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EPE_WRITE(RXStsEnq, ndq);
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EPE_WRITE(RXDEnq, ndq);
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ndq = 0;
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}
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if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) {
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epe_ifstart(ifp);
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}
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irq = EPE_READ(IntStsC);
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if ((irq & (IntSts_RxSQ|IntSts_ECI)) != 0)
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goto begin;
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return (1);
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}
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static void
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epe_init(struct epe_softc *sc)
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{
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bus_dma_segment_t segs;
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caddr_t addr;
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int rsegs, err, i;
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struct ifnet * ifp = &sc->sc_ec.ec_if;
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callout_init(&sc->epe_tick_ch);
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/* Select primary Individual Address in Address Filter Pointer */
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EPE_WRITE(AFP, 0);
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/* Read ethernet MAC, should already be set by bootrom */
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bus_space_read_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
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sc->sc_enaddr, ETHER_ADDR_LEN);
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printf("%s: MAC address %s\n", sc->sc_dev.dv_xname,
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ether_sprintf(sc->sc_enaddr));
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/* Soft Reset the MAC */
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EPE_WRITE(SelfCtl, SelfCtl_RESET);
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while(EPE_READ(SelfCtl) & SelfCtl_RESET);
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/* suggested magic initialization values from datasheet */
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EPE_WRITE(RXBufThrshld, 0x800040);
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EPE_WRITE(TXBufThrshld, 0x200010);
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EPE_WRITE(RXStsThrshld, 0x40002);
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EPE_WRITE(TXStsThrshld, 0x40002);
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EPE_WRITE(RXDThrshld, 0x40002);
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EPE_WRITE(TXDThrshld, 0x40002);
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/* Allocate a page of memory for descriptor and status queues */
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err = bus_dmamem_alloc(sc->sc_dmat, PAGE_SIZE, 0, PAGE_SIZE,
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&segs, 1, &rsegs, BUS_DMA_WAITOK);
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if (err == 0) {
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err = bus_dmamem_map(sc->sc_dmat, &segs, 1, PAGE_SIZE,
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&sc->ctrlpage, (BUS_DMA_WAITOK|BUS_DMA_COHERENT));
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}
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if (err == 0) {
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err = bus_dmamap_create(sc->sc_dmat, PAGE_SIZE, 1, PAGE_SIZE,
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0, BUS_DMA_WAITOK, &sc->ctrlpage_dmamap);
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}
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if (err == 0) {
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err = bus_dmamap_load(sc->sc_dmat, sc->ctrlpage_dmamap,
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sc->ctrlpage, PAGE_SIZE, NULL, BUS_DMA_WAITOK);
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}
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if (err != 0) {
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panic("%s: Cannot get DMA memory", sc->sc_dev.dv_xname);
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}
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sc->ctrlpage_dsaddr = sc->ctrlpage_dmamap->dm_segs[0].ds_addr;
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bzero(sc->ctrlpage, PAGE_SIZE);
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/* Set up pointers to start of each queue in kernel addr space.
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* Each descriptor queue or status queue entry uses 2 words
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*/
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sc->TXDQ = (u_int32_t *)sc->ctrlpage;
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sc->TXDQ_cur = sc->TXDQ;
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sc->TXDQ_avail = TX_QLEN - 1;
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sc->TXStsQ = &sc->TXDQ[TX_QLEN * 2];
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sc->TXStsQ_cur = sc->TXStsQ;
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sc->RXDQ = &sc->TXStsQ[TX_QLEN];
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sc->RXStsQ = &sc->RXDQ[RX_QLEN * 2];
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sc->RXStsQ_cur = sc->RXStsQ;
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/* Program each queue's start addr, cur addr, and len registers
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* with the physical addresses.
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*/
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addr = (caddr_t)sc->ctrlpage_dmamap->dm_segs[0].ds_addr;
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EPE_WRITE(TXDQBAdd, (u_int32_t)addr);
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EPE_WRITE(TXDQCurAdd, (u_int32_t)addr);
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EPE_WRITE(TXDQBLen, TX_QLEN * 2 * sizeof(u_int32_t));
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addr += (sc->TXStsQ - sc->TXDQ) * sizeof(u_int32_t);
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EPE_WRITE(TXStsQBAdd, (u_int32_t)addr);
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EPE_WRITE(TXStsQCurAdd, (u_int32_t)addr);
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EPE_WRITE(TXStsQBLen, TX_QLEN * sizeof(u_int32_t));
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addr += (sc->RXDQ - sc->TXStsQ) * sizeof(u_int32_t);
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EPE_WRITE(RXDQBAdd, (u_int32_t)addr);
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EPE_WRITE(RXDCurAdd, (u_int32_t)addr);
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EPE_WRITE(RXDQBLen, RX_QLEN * 2 * sizeof(u_int32_t));
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addr += (sc->RXStsQ - sc->RXDQ) * sizeof(u_int32_t);
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EPE_WRITE(RXStsQBAdd, (u_int32_t)addr);
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EPE_WRITE(RXStsQCurAdd, (u_int32_t)addr);
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EPE_WRITE(RXStsQBLen, RX_QLEN * 2 * sizeof(u_int32_t));
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/* Populate the RXDQ with mbufs */
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for(i = 0; i < RX_QLEN; i++) {
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struct mbuf *m;
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bus_dmamap_create(sc->sc_dmat, MCLBYTES, TX_QLEN/4, MCLBYTES, 0,
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BUS_DMA_WAITOK, &sc->rxq[i].m_dmamap);
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MGETHDR(m, M_WAIT, MT_DATA);
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MCLGET(m, M_WAIT);
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sc->rxq[i].m = m;
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bus_dmamap_load(sc->sc_dmat, sc->rxq[i].m_dmamap,
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m->m_ext.ext_buf, MCLBYTES, NULL,
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BUS_DMA_WAITOK);
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sc->RXDQ[i * 2] = sc->rxq[i].m_dmamap->dm_segs[0].ds_addr;
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sc->RXDQ[i * 2 + 1] = (i << 16) | MCLBYTES;
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bus_dmamap_sync(sc->sc_dmat, sc->rxq[i].m_dmamap, 0,
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MCLBYTES, BUS_DMASYNC_PREREAD);
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}
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for(i = 0; i < TX_QLEN; i++) {
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bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
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(BUS_DMA_WAITOK|BUS_DMA_ALLOCNOW),
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&sc->txq[i].m_dmamap);
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sc->txq[i].m = NULL;
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sc->TXDQ[i * 2 + 1] = (i << 16);
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}
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/* Divide HCLK by 32 for MDC clock */
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EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(32)|SelfCtl_PSPRS));
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sc->sc_mii.mii_ifp = ifp;
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sc->sc_mii.mii_readreg = epe_mii_readreg;
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sc->sc_mii.mii_writereg = epe_mii_writereg;
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sc->sc_mii.mii_statchg = epe_statchg;
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ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epe_mediachange,
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epe_mediastatus);
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mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
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MII_OFFSET_ANY, 0);
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ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
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EPE_WRITE(BMCtl, BMCtl_RxEn|BMCtl_TxEn);
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EPE_WRITE(IntEn, IntEn_REOFIE);
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/* maximum valid max frame length */
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EPE_WRITE(MaxFrmLen, (0x7ff << 16)|MHLEN);
|
|
/* wait for receiver ready */
|
|
while((EPE_READ(BMSts) & BMSts_RxAct) == 0);
|
|
/* enqueue the entries in RXStsQ and RXDQ */
|
|
CTRLPAGE_DMASYNC(0, sc->ctrlpage_dmamap->dm_mapsize,
|
|
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
|
|
EPE_WRITE(RXDEnq, RX_QLEN - 1);
|
|
EPE_WRITE(RXStsEnq, RX_QLEN - 1);
|
|
|
|
/*
|
|
* We can support 802.1Q VLAN-sized frames.
|
|
*/
|
|
sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
|
|
|
|
strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
|
|
ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_NOTRAILERS|IFF_MULTICAST;
|
|
ifp->if_ioctl = epe_ifioctl;
|
|
ifp->if_start = epe_ifstart;
|
|
ifp->if_watchdog = epe_ifwatchdog;
|
|
ifp->if_init = epe_ifinit;
|
|
ifp->if_stop = epe_ifstop;
|
|
ifp->if_timer = 0;
|
|
ifp->if_softc = sc;
|
|
IFQ_SET_READY(&ifp->if_snd);
|
|
if_attach(ifp);
|
|
ether_ifattach(ifp, (sc)->sc_enaddr);
|
|
}
|
|
|
|
static int
|
|
epe_mediachange(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
if (ifp->if_flags & IFF_UP)
|
|
epe_ifinit(ifp);
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
epe_mediastatus(ifp, ifmr)
|
|
struct ifnet *ifp;
|
|
struct ifmediareq *ifmr;
|
|
{
|
|
struct epe_softc *sc = ifp->if_softc;
|
|
|
|
mii_pollstat(&sc->sc_mii);
|
|
ifmr->ifm_active = sc->sc_mii.mii_media_active;
|
|
ifmr->ifm_status = sc->sc_mii.mii_media_status;
|
|
}
|
|
|
|
|
|
int
|
|
epe_mii_readreg(self, phy, reg)
|
|
struct device *self;
|
|
int phy, reg;
|
|
{
|
|
u_int32_t d, v;
|
|
struct epe_softc *sc;
|
|
|
|
sc = (struct epe_softc *)self;
|
|
d = EPE_READ(SelfCtl);
|
|
EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */
|
|
EPE_WRITE(MIICmd, (MIICmd_READ | (phy << 5) | reg));
|
|
while(EPE_READ(MIISts) & MIISts_BUSY);
|
|
v = EPE_READ(MIIData);
|
|
EPE_WRITE(SelfCtl, d); /* restore old value */
|
|
return v;
|
|
}
|
|
|
|
void
|
|
epe_mii_writereg(self, phy, reg, val)
|
|
struct device *self;
|
|
int phy, reg, val;
|
|
{
|
|
struct epe_softc *sc;
|
|
u_int32_t d;
|
|
|
|
sc = (struct epe_softc *)self;
|
|
d = EPE_READ(SelfCtl);
|
|
EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */
|
|
EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg));
|
|
EPE_WRITE(MIIData, val);
|
|
while(EPE_READ(MIISts) & MIISts_BUSY);
|
|
EPE_WRITE(SelfCtl, d); /* restore old value */
|
|
}
|
|
|
|
|
|
void
|
|
epe_statchg(self)
|
|
struct device *self;
|
|
{
|
|
struct epe_softc *sc = (struct epe_softc *)self;
|
|
u_int32_t reg;
|
|
|
|
/*
|
|
* We must keep the MAC and the PHY in sync as
|
|
* to the status of full-duplex!
|
|
*/
|
|
reg = EPE_READ(TestCtl);
|
|
if (sc->sc_mii.mii_media_active & IFM_FDX)
|
|
reg |= TestCtl_MFDX;
|
|
else
|
|
reg &= ~TestCtl_MFDX;
|
|
EPE_WRITE(TestCtl, reg);
|
|
}
|
|
|
|
void
|
|
epe_tick(arg)
|
|
void *arg;
|
|
{
|
|
struct epe_softc* sc = (struct epe_softc *)arg;
|
|
struct ifnet * ifp = &sc->sc_ec.ec_if;
|
|
int s;
|
|
u_int32_t misses;
|
|
|
|
ifp->if_collisions += EPE_READ(TXCollCnt);
|
|
/* These misses are ok, they will happen if the RAM/CPU can't keep up */
|
|
misses = EPE_READ(RXMissCnt);
|
|
if (misses > 0)
|
|
printf("%s: %d rx misses\n", sc->sc_dev.dv_xname, misses);
|
|
|
|
s = splnet();
|
|
if (epe_gctx(sc) > 0 && IFQ_IS_EMPTY(&ifp->if_snd) == 0) {
|
|
epe_ifstart(ifp);
|
|
}
|
|
splx(s);
|
|
|
|
mii_tick(&sc->sc_mii);
|
|
callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc);
|
|
}
|
|
|
|
|
|
static int
|
|
epe_ifioctl(ifp, cmd, data)
|
|
struct ifnet *ifp;
|
|
u_long cmd;
|
|
caddr_t data;
|
|
{
|
|
struct epe_softc *sc = ifp->if_softc;
|
|
struct ifreq *ifr = (struct ifreq *)data;
|
|
int s, error;
|
|
|
|
s = splnet();
|
|
switch(cmd) {
|
|
case SIOCSIFMEDIA:
|
|
case SIOCGIFMEDIA:
|
|
error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
|
|
break;
|
|
default:
|
|
error = ether_ioctl(ifp, cmd, data);
|
|
if (error == ENETRESET) {
|
|
if (ifp->if_flags & IFF_RUNNING)
|
|
epe_setaddr(ifp);
|
|
error = 0;
|
|
}
|
|
}
|
|
splx(s);
|
|
return error;
|
|
}
|
|
|
|
static void
|
|
epe_ifstart(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct epe_softc *sc = (struct epe_softc *)ifp->if_softc;
|
|
struct mbuf *m;
|
|
bus_dma_segment_t *segs;
|
|
int s, bi, err, nsegs, ndq;
|
|
|
|
s = splnet();
|
|
start:
|
|
ndq = 0;
|
|
if (sc->TXDQ_avail == 0) {
|
|
if (epe_gctx(sc) == 0) {
|
|
/* Enable End-Of-TX-Chain interrupt */
|
|
EPE_WRITE(IntEn, IntEn_REOFIE|IntEn_ECIE);
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
ifp->if_timer = 10;
|
|
splx(s);
|
|
return;
|
|
}
|
|
}
|
|
|
|
bi = sc->TXDQ_cur - sc->TXDQ;
|
|
|
|
IFQ_POLL(&ifp->if_snd, m);
|
|
if (m == NULL) {
|
|
splx(s);
|
|
return;
|
|
}
|
|
more:
|
|
if ((err = bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m,
|
|
BUS_DMA_NOWAIT)) ||
|
|
sc->txq[bi].m_dmamap->dm_segs[0].ds_addr & 0x3 ||
|
|
sc->txq[bi].m_dmamap->dm_nsegs > (sc->TXDQ_avail - ndq)) {
|
|
/* Copy entire mbuf chain to new and 32-bit aligned storage */
|
|
struct mbuf *mn;
|
|
|
|
if (err == 0)
|
|
bus_dmamap_unload(sc->sc_dmat, sc->txq[bi].m_dmamap);
|
|
|
|
MGETHDR(mn, M_DONTWAIT, MT_DATA);
|
|
if (mn == NULL) goto stop;
|
|
if (m->m_pkthdr.len > (MHLEN & (~0x3))) {
|
|
MCLGET(mn, M_DONTWAIT);
|
|
if ((mn->m_flags & M_EXT) == 0) {
|
|
m_freem(mn);
|
|
goto stop;
|
|
}
|
|
}
|
|
mn->m_data = (caddr_t)(((u_int32_t)mn->m_data + 0x3) & (~0x3));
|
|
m_copydata(m, 0, m->m_pkthdr.len, mtod(mn, caddr_t));
|
|
mn->m_pkthdr.len = mn->m_len = m->m_pkthdr.len;
|
|
IFQ_DEQUEUE(&ifp->if_snd, m);
|
|
m_freem(m);
|
|
m = mn;
|
|
bus_dmamap_load_mbuf(sc->sc_dmat, sc->txq[bi].m_dmamap, m,
|
|
BUS_DMA_NOWAIT);
|
|
} else {
|
|
IFQ_DEQUEUE(&ifp->if_snd, m);
|
|
}
|
|
|
|
#if NBPFILTER > 0
|
|
if (ifp->if_bpf)
|
|
bpf_mtap(ifp->if_bpf, m);
|
|
#endif /* NBPFILTER > 0 */
|
|
|
|
nsegs = sc->txq[bi].m_dmamap->dm_nsegs;
|
|
segs = sc->txq[bi].m_dmamap->dm_segs;
|
|
bus_dmamap_sync(sc->sc_dmat, sc->txq[bi].m_dmamap, 0,
|
|
sc->txq[bi].m_dmamap->dm_mapsize,
|
|
BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
|
|
|
|
/* XXX: This driver hasn't been tested w/nsegs > 1 */
|
|
while (nsegs > 0) {
|
|
nsegs--;
|
|
sc->txq[bi].m = m;
|
|
sc->TXDQ[bi * 2] = segs->ds_addr;
|
|
if (nsegs == 0)
|
|
sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16) |
|
|
(1 << 31);
|
|
else
|
|
sc->TXDQ[bi * 2 + 1] = segs->ds_len | (bi << 16);
|
|
segs++;
|
|
bi = (bi + 1) % TX_QLEN;
|
|
ndq++;
|
|
}
|
|
|
|
|
|
/*
|
|
* Enqueue another. Don't do more than half the available
|
|
* descriptors before telling the MAC about them
|
|
*/
|
|
if ((sc->TXDQ_avail - ndq) > 0 && ndq < TX_QLEN / 2) {
|
|
IFQ_POLL(&ifp->if_snd, m);
|
|
if (m != NULL) {
|
|
goto more;
|
|
}
|
|
}
|
|
stop:
|
|
if (ndq > 0) {
|
|
sc->TXDQ_avail -= ndq;
|
|
sc->TXDQ_cur = &sc->TXDQ[bi];
|
|
CTRLPAGE_DMASYNC(0, TX_QLEN * 2 * sizeof(u_int32_t),
|
|
BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
|
|
EPE_WRITE(TXDEnq, ndq);
|
|
}
|
|
|
|
if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
|
|
goto start;
|
|
|
|
splx(s);
|
|
return;
|
|
}
|
|
|
|
static void
|
|
epe_ifwatchdog(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct epe_softc *sc = (struct epe_softc *)ifp->if_softc;
|
|
|
|
if ((ifp->if_flags & IFF_RUNNING) == 0)
|
|
return;
|
|
printf("%s: device timeout, BMCtl = 0x%08x, BMSts = 0x%08x\n",
|
|
sc->sc_dev.dv_xname, EPE_READ(BMCtl), EPE_READ(BMSts));
|
|
}
|
|
|
|
static int
|
|
epe_ifinit(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct epe_softc *sc = ifp->if_softc;
|
|
int s = splnet();
|
|
|
|
callout_stop(&sc->epe_tick_ch);
|
|
EPE_WRITE(RXCtl, RXCtl_IA0|RXCtl_BA|RXCtl_RCRCA|RXCtl_SRxON);
|
|
EPE_WRITE(TXCtl, TXCtl_STxON);
|
|
EPE_WRITE(GIIntMsk, GIIntMsk_INT); /* start interrupting */
|
|
mii_mediachg(&sc->sc_mii);
|
|
callout_reset(&sc->epe_tick_ch, hz, epe_tick, sc);
|
|
ifp->if_flags |= IFF_RUNNING;
|
|
splx(s);
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
epe_ifstop(ifp, disable)
|
|
struct ifnet *ifp;
|
|
int disable;
|
|
{
|
|
struct epe_softc *sc = ifp->if_softc;
|
|
|
|
|
|
EPE_WRITE(RXCtl, 0);
|
|
EPE_WRITE(TXCtl, 0);
|
|
EPE_WRITE(GIIntMsk, 0);
|
|
callout_stop(&sc->epe_tick_ch);
|
|
|
|
/* Down the MII. */
|
|
mii_down(&sc->sc_mii);
|
|
|
|
ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
|
|
ifp->if_timer = 0;
|
|
sc->sc_mii.mii_media_status &= ~IFM_ACTIVE;
|
|
}
|
|
|
|
static void
|
|
epe_setaddr(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct epe_softc *sc = ifp->if_softc;
|
|
struct ethercom *ac = &sc->sc_ec;
|
|
struct ether_multi *enm;
|
|
struct ether_multistep step;
|
|
u_int8_t ias[2][ETHER_ADDR_LEN];
|
|
u_int32_t h, nma = 0, hashes[2] = { 0, 0 };
|
|
u_int32_t rxctl = EPE_READ(RXCtl);
|
|
|
|
/* disable receiver temporarily */
|
|
EPE_WRITE(RXCtl, rxctl & ~RXCtl_SRxON);
|
|
|
|
rxctl &= ~(RXCtl_MA|RXCtl_PA|RXCtl_IA2|RXCtl_IA3);
|
|
|
|
if (ifp->if_flags & IFF_PROMISC) {
|
|
rxctl |= RXCtl_PA;
|
|
}
|
|
|
|
ifp->if_flags &= ~IFF_ALLMULTI;
|
|
|
|
ETHER_FIRST_MULTI(step, ac, enm);
|
|
while (enm != NULL) {
|
|
if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
|
|
/*
|
|
* We must listen to a range of multicast addresses.
|
|
* For now, just accept all multicasts, rather than
|
|
* trying to set only those filter bits needed to match
|
|
* the range. (At this time, the only use of address
|
|
* ranges is for IP multicast routing, for which the
|
|
* range is big enough to require all bits set.)
|
|
*/
|
|
rxctl &= ~(RXCtl_IA2|RXCtl_IA3);
|
|
rxctl |= RXCtl_MA;
|
|
hashes[0] = 0xffffffffUL;
|
|
hashes[1] = 0xffffffffUL;
|
|
ifp->if_flags |= IFF_ALLMULTI;
|
|
break;
|
|
}
|
|
|
|
if (nma < 2) {
|
|
/* We can program 2 perfect address filters for mcast */
|
|
memcpy(ias[nma], enm->enm_addrlo, ETHER_ADDR_LEN);
|
|
rxctl |= (1 << (nma + 2));
|
|
} else {
|
|
/*
|
|
* XXX: Datasheet is not very clear here, I'm not sure
|
|
* if I'm doing this right. --joff
|
|
*/
|
|
h = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
|
|
|
|
/* Just want the 6 most-significant bits. */
|
|
h = h >> 26;
|
|
|
|
hashes[ h / 32 ] |= (1 << (h % 32));
|
|
rxctl |= RXCtl_MA;
|
|
}
|
|
ETHER_NEXT_MULTI(step, enm);
|
|
nma++;
|
|
}
|
|
|
|
EPE_WRITE(AFP, 0);
|
|
bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
|
|
sc->sc_enaddr, ETHER_ADDR_LEN);
|
|
if (rxctl & RXCtl_IA2) {
|
|
EPE_WRITE(AFP, 2);
|
|
bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
|
|
ias[0], ETHER_ADDR_LEN);
|
|
}
|
|
if (rxctl & RXCtl_IA3) {
|
|
EPE_WRITE(AFP, 3);
|
|
bus_space_write_region_1(sc->sc_iot, sc->sc_ioh, EPE_IndAd,
|
|
ias[1], ETHER_ADDR_LEN);
|
|
}
|
|
if (hashes[0] != 0 && hashes[1] != 0) {
|
|
EPE_WRITE(AFP, 7);
|
|
EPE_WRITE(HashTbl, hashes[0]);
|
|
EPE_WRITE(HashTbl + 4, hashes[1]);
|
|
}
|
|
EPE_WRITE(RXCtl, rxctl);
|
|
}
|