217 lines
7.6 KiB
C
217 lines
7.6 KiB
C
/* $NetBSD: ep93xxreg.h,v 1.4 2005/08/14 03:07:30 joff Exp $ */
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/*
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* Copyright (c) 2004 Jesse Off
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _EP93XXREG_H_
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#define _EP93XXREG_H_
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/*
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* Physical memory map for the Cirrus Logic EP93XX
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*/
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/*
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* FFFF FFFF ---------------------------
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* Device 12
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* External SMC CS#0 ROM/SRAM
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* F000 0000 ---------------------------
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* Device 11
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* SDRAM CS#2
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* E000 0000 ---------------------------
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* Device 10
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* SDRAM CS#1
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* D000 0000 ---------------------------
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* Device 9
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* SDRAM CS#0
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* C000 0000 ---------------------------
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* Device 8
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* Not used
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* 9000 0000 ---------------------------
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* Device 7
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* EP93XX System Registers
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* 8080 0000 - 8094 FFFF
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* APB Mapped Registers
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* 8010 0000 - 807F FFFF
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* Reserved
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* 8000 0000 - 800F FFFF
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* AHB Mapped Registers
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* 8000 0000 ---------------------------
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* Device 6
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* External SMC CS#7 ROM/SRAM
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* 7000 0000 ---------------------------
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* Device 5
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* External SMC CS#6 ROM/SRAM
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* 6000 0000 ---------------------------
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* Device 4
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* Reserved
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* 4000 0000 ---------------------------
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* Device 3
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* External SMC CS#3 ROM/SRAM
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* 3000 0000 ---------------------------
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* Device 2
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* External SMC CS#2 ROM/SRAM
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* 2000 0000 ---------------------------
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* Device 1
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* External SMC CS#1 ROM/SRAM
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* 1000 0000 ---------------------------
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* Device 0
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* SDRAM CS#3
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* 0000 0000 ---------------------------
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*/
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/*
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* Virtual memory map for the Cirrus Logic EP93XX integrated devices
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*
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* Some device registers are staticaly mapped on upper address region.
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* because we have to access them before bus_space is initialized.
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* Most device is dynamicaly mapped by bus_space_map(). In this case,
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* the actual mapped (virtual) address are not cared by device drivers.
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*/
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/*
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* FFFF FFFF ---------------------------
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* not used
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* F030 0000 ---------------------------
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* APB bus (2Mbyte)
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* F010 0000 ---------------------------
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* AHB bus (1Mbyte)
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* F000 0000 ---------------------------
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* Kernel text and data
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* C000 0000 ---------------------------
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* 0000 0000 ---------------------------
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*
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*/
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/* Virtual address for I/O space */
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#define EP93XX_IO_VBASE 0xf0000000UL
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/* EP93xx System and Peripheral Registers */
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#define EP93XX_AHB_VBASE 0xf0000000UL
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#define EP93XX_AHB_HWBASE 0x80000000UL
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#define EP93XX_AHB_SIZE 0x00100000UL /* 1Mbyte */
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#define EP93XX_AHB_VIC1 0x000b0000UL
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#define EP93XX_AHB_VIC2 0x000c0000UL
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#define EP93XX_VIC_IRQStatus 0x00000000UL
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#define EP93XX_VIC_FIQStatus 0x00000004UL
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#define EP93XX_VIC_RawIntr 0x00000008UL
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#define EP93XX_VIC_IntSelect 0x0000000cUL
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#define EP93XX_VIC_IntEnable 0x00000010UL
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#define EP93XX_VIC_IntEnClear 0x00000014UL
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#define EP93XX_VIC_SoftInt 0x00000018UL
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#define EP93XX_VIC_SoftIntClear 0x0000001cUL
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#define EP93XX_VIC_Protection 0x00000020UL
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#define EP93XX_VIC_VectAddr 0x00000030UL
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#define EP93XX_VIC_DefVectAddr 0x00000034UL
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#define EP93XX_VIC_VectAddr0 0x00000100UL
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#define EP93XX_VIC_VectCntl0 0x00000200UL
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#define EP93XX_VIC_PeriphID0 0x00000fe0UL
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#define EP93XX_APB_VBASE 0xf0100000UL
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#define EP93XX_APB_HWBASE 0x80800000UL
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#define EP93XX_APB_SIZE 0x00200000UL /* 2Mbyte */
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#define EP93XX_APB_GPIO 0x00040000UL
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#define EP93XX_APB_GPIO_SIZE 0x000000d0UL
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#define EP93XX_GPIO_PADR 0x00000000UL
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#define EP93XX_GPIO_PBDR 0x00000004UL
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#define EP93XX_GPIO_PADDR 0x00000010UL
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#define EP93XX_GPIO_PBDDR 0x00000014UL
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#define EP93XX_GPIO_PFDR 0x00000030UL
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#define EP93XX_GPIO_PFDDR 0x00000034UL
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#define EP93XX_GPIO_PHDR 0x00000040UL
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#define EP93XX_GPIO_PHDDR 0x00000044UL
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#define EP93XX_APB_SSP 0x000a0000UL
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#define EP93XX_APB_SSP_SIZE 0x00000018UL
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#define EP93XX_SSP_SSPCR0 0x00000000UL
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#define EP93XX_SSP_SSPCR1 0x00000004UL
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#define EP93XX_SSP_SSPDR 0x00000008UL
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#define EP93XX_SSP_SSPSR 0x0000000cUL
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#define EP93XX_SSP_SSPCPSR 0x00000010UL
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#define EP93XX_SSP_SSPIIR 0x00000014UL
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#define EP93XX_SSP_SSPICR 0x00000014UL
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#define EP93XX_APB_SYSCON 0x00130000UL
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#define EP93XX_APB_SYSCON_SIZE 0x000000c0UL
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#define EP93XX_SYSCON_PwrSts 0x00000000UL
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#define EP93XX_SYSCON_PwrCnt 0x00000004UL
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#define PwrCnt_UARTBAUD 0x20000000UL
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#define EP93XX_SYSCON_TEOI 0x00000018UL
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#define EP93XX_SYSCON_ClkSet1 0x00000020UL
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#define EP93XX_SYSCON_ClkSet2 0x00000024UL
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#define EP93XX_SYSCON_ChipID 0x00000094UL
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#define EP93XX_APB_TIMERS 0x00010000UL
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#define EP93XX_TIMERS_Timer4Enable 0x00000064UL
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#define EP93XX_TIMERS_Timer4ValueHigh 0x00000064UL
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#define EP93XX_TIMERS_Timer4ValueLow 0x00000060UL
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#define EP93XX_APB_UART1 0x000c0000UL
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#define EP93XX_APB_UART2 0x000d0000UL
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#define EP93XX_APB_UART_SIZE 0x00000220UL
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#define EP93XX_UART_Flag 0x00000018UL
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#define EP93XX_UART_Data 0x00000000UL
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#define NIRQ 64
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#define VIC_NIRQ 32
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#define EP93XX_INTR_bit31 31
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#define EP93XX_INTR_bit30 30
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#define EP93XX_INTR_bit29 29
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#define EP93XX_INTR_bit28 28
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#define EP93XX_INTR_bit27 27
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#define EP93XX_INTR_bit26 26
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#define EP93XX_INTR_bit25 25
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#define EP93XX_INTR_bit24 24
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#define EP93XX_INTR_bit23 23
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#define EP93XX_INTR_bit22 22
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#define EP93XX_INTR_bit21 21
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#define EP93XX_INTR_bit20 20
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#define EP93XX_INTR_bit19 19
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#define EP93XX_INTR_bit18 18
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#define EP93XX_INTR_bit17 17
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#define EP93XX_INTR_bit16 16
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#define EP93XX_INTR_bit15 15
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#define EP93XX_INTR_bit14 14
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#define EP93XX_INTR_bit13 13
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#define EP93XX_INTR_bit12 12
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#define EP93XX_INTR_bit11 11
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#define EP93XX_INTR_bit10 10
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#define EP93XX_INTR_bit9 9
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#define EP93XX_INTR_bit8 8
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#define EP93XX_INTR_bit7 7
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#define EP93XX_INTR_bit6 6
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#define EP93XX_INTR_bit5 5
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#define EP93XX_INTR_bit4 4
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#define EP93XX_INTR_bit3 3
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#define EP93XX_INTR_bit2 2
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#define EP93XX_INTR_bit1 1
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#define EP93XX_INTR_bit0 0
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#endif /* _EP93XXREG_H_ */
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