531 lines
20 KiB
C
531 lines
20 KiB
C
/* $NetBSD: tx39icureg.h,v 1.2 1999/12/26 17:05:28 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* TOSHIBA TMPR3912/3922 interrupt module.
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*/
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#ifdef TX391X
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#define TX39_INTRSET_MAX 5
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#endif /* TX391X */
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#ifdef TX392X
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#define TX39_INTRSET_MAX 8
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#endif /* TX391X */
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#define TX39_IRQHIGH_MAX 16
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/* R */
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#define TX39_INTRSTATUS1_REG 0x100
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#define TX39_INTRSTATUS2_REG 0x104
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#define TX39_INTRSTATUS3_REG 0x108
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#define TX39_INTRSTATUS4_REG 0x10c
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#define TX39_INTRSTATUS5_REG 0x110
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#define TX39_INTRSTATUS6_REG 0x114
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#ifdef TX392X
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#define TX39_INTRSTATUS7_REG 0x130
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#define TX39_INTRSTATUS8_REG 0x138
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#endif /* TX392X */
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#ifdef TX391X
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#define TX39_INTRSTATUS_REG(x) (((x) - 1) * 4 + TX39_INTRSTATUS1_REG)
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#endif /* TX391X */
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#ifdef TX392X
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#define TX39_INTRSTATUS_REG(x) (((x) <= 6) ? \
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(((x) - 1) * 4 + TX39_INTRSTATUS1_REG) : \
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(((x) - 7) * 8 + TX39_INTRSTATUS7_REG))
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#endif /* TX392X */
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/* W */
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#define TX39_INTRCLEAR1_REG 0x100
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#define TX39_INTRCLEAR2_REG 0x104
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#define TX39_INTRCLEAR3_REG 0x108
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#define TX39_INTRCLEAR4_REG 0x10c
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#define TX39_INTRCLEAR5_REG 0x110
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#ifdef TX392X
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#define TX39_INTRCLEAR7_REG 0x130
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#define TX39_INTRCLEAR8_REG 0x138
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#endif /* TX392X */
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#ifdef TX391X
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#define TX39_INTRCLEAR_REG(x) (((x) - 1) * 4 + TX39_INTRCLEAR1_REG)
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#endif /* TX391X */
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#ifdef TX392X
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#define TX39_INTRCLEAR_REG(x) (((x) <= 6) ? \
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(((x) - 1) * 4 + TX39_INTRCLEAR1_REG) : \
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(((x) - 7) * 8 + TX39_INTRCLEAR7_REG))
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#endif /* TX392X */
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/* R/W */
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#define TX39_INTRENABLE1_REG 0x118
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#define TX39_INTRENABLE2_REG 0x11c
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#define TX39_INTRENABLE3_REG 0x120
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#define TX39_INTRENABLE4_REG 0x124
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#define TX39_INTRENABLE5_REG 0x128
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#define TX39_INTRENABLE6_REG 0x12c
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#ifdef TX392X
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#define TX39_INTRENABLE7_REG 0x134
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#define TX39_INTRENABLE8_REG 0x13c
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#endif /* TX392X */
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#ifdef TX391X
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#define TX39_INTRENABLE_REG(x) (((x) - 1) * 4 + TX39_INTRENABLE1_REG)
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#endif /* TX391X */
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#ifdef TX392X
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#define TX39_INTRENABLE_REG(x) (((x) <= 6) ? \
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(((x) - 1) * 4 + TX39_INTRENABLE1_REG) : \
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(((x) - 7) * 8 + TX39_INTRENABLE7_REG))
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#endif /* TX392X */
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/*
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* IRQLOW
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*/
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/*
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* Interrupt status/clear 1 register.
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* -> Enable 1 register
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*/
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/* R/W */
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#ifdef TX391X
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#define TX39_INTRSTATUS1_LCDINT 0x80000000
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#define TX39_INTRSTATUS1_DFINT 0x40000000
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#endif /* TX391X */
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#define TX39_INTRSTATUS1_CHI0_5INT 0x20000000
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#define TX39_INTRSTATUS1_CHI1_0INT 0x10000000
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#define TX39_INTRSTATUS1_CHIDMACNTINT 0x08000000
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#define TX39_INTRSTATUS1_CHININTA 0x04000000
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#define TX39_INTRSTATUS1_CHININTB 0x02000000
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#define TX39_INTRSTATUS1_CHIACTINT 0x01000000
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#define TX39_INTRSTATUS1_CHIERRINT 0x00800000
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#define TX39_INTRSTATUS1_SND0_5INT 0x00400000
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#define TX39_INTRSTATUS1_SND1_0INT 0x00200000
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#define TX39_INTRSTATUS1_TEL0_5INT 0x00100000
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#define TX39_INTRSTATUS1_TEL1_0INT 0x00080000
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#define TX39_INTRSTATUS1_SNDDMACNTINT 0x00040000
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#define TX39_INTRSTATUS1_TELDMACNTINT 0x00020000
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#define TX39_INTRSTATUS1_LSNDCLIPINT 0x00010000
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#define TX39_INTRSTATUS1_RSNDCLIPINT 0x00008000
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#define TX39_INTRSTATUS1_VALSNDPOSINT 0x00004000
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#define TX39_INTRSTATUS1_VALSNDNEGINT 0x00002000
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#define TX39_INTRSTATUS1_VALTELPOSINT 0x00001000
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#define TX39_INTRSTATUS1_VALTELNEGINT 0x00000800
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#define TX39_INTRSTATUS1_SNDININT 0x00000400
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#define TX39_INTRSTATUS1_TELININT 0x00000200
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#define TX39_INTRSTATUS1_SIBSF0INT 0x00000100
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#define TX39_INTRSTATUS1_SIBSF1INT 0x00000080
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#define TX39_INTRSTATUS1_SIBIRQPOSINT 0x00000040
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#define TX39_INTRSTATUS1_SIBIRQNEGINT 0x00000020
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#ifdef TX391X
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#define TX39_INTRSTATUS1_VIDEO 0xc0000000
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#endif /* TX391X */
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#define TX39_INTRSTATUS1_CHI 0x3f800000
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#define TX39_INTRSTATUS1_SND 0x007ffe00
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#define TX39_INTRSTATUS1_SIB 0x000001e0
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/*
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* Interrupt status/clear 2 register.
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* -> Enable 2 register
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*/
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/* R/W */
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#define TX39_INTRSTATUS2_UARTARXINT 0x80000000
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#define TX39_INTRSTATUS2_UARTARXOVERRUNINT 0x40000000
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#define TX39_INTRSTATUS2_UARTAFRAMEERRINT 0x20000000
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#define TX39_INTRSTATUS2_UARTABREAKINT 0x10000000
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#define TX39_INTRSTATUS2_UARTAPARITYERRINT 0x08000000
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#define TX39_INTRSTATUS2_UARTATXINT 0x04000000
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#define TX39_INTRSTATUS2_UARTATXOVERRUNINT 0x02000000
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#define TX39_INTRSTATUS2_UARTAEMPTYINT 0x01000000
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#define TX39_INTRSTATUS2_UARTADMAFULLINT 0x00800000
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#define TX39_INTRSTATUS2_UARTADMAHALFINT 0x00400000
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#define TX39_INTRSTATUS2_UARTBRXINT 0x00200000
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#define TX39_INTRSTATUS2_UARTBRXOVERRUNINT 0x00100000
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#define TX39_INTRSTATUS2_UARTBFRAMEERRINT 0x00080000
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#define TX39_INTRSTATUS2_UARTBBREAKINT 0x00040000
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#define TX39_INTRSTATUS2_UARTBPARITYERRINT 0x00020000
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#define TX39_INTRSTATUS2_UARTBTXINT 0x00010000
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#define TX39_INTRSTATUS2_UARTBTXOVERRUNINT 0x00008000
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#define TX39_INTRSTATUS2_UARTBEMPTYINT 0x00004000
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#define TX39_INTRSTATUS2_UARTBDMAFULLINT 0x00002000
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#define TX39_INTRSTATUS2_UARTBDMAHALFINT 0x00001000
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#define TX39_INTRSTATUS2_UARTRXINT(x) \
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((x) ? TX39_INTRSTATUS2_UARTBRXINT : \
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TX39_INTRSTATUS2_UARTARXINT)
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#define TX39_INTRSTATUS2_UARTRXOVERRUNINT(x) \
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((x) ? TX39_INTRSTATUS2_UARTBRXOVERRUNINT : \
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TX39_INTRSTATUS2_UARTARXOVERRUNINT)
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#define TX39_INTRSTATUS2_UARTFRAMEERRINT(x) \
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((x) ? TX39_INTRSTATUS2_UARTBFRAMEERRINT : \
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TX39_INTRSTATUS2_UARTAFRAMEERRINT)
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#define TX39_INTRSTATUS2_UARTBREAKINT(x) \
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((x) ? TX39_INTRSTATUS2_UARTBBREAKINT : \
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TX39_INTRSTATUS2_UARTABREAKINT)
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#define TX39_INTRSTATUS2_UARTPARITYERRINT(x) \
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((x) ? TX39_INTRSTATUS2_UARTBPARITYERRINT : \
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TX39_INTRSTATUS2_UARTAPARITYERRINT)
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#define TX39_INTRSTATUS2_UARTTXINT(x) \
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((x) ? TX39_INTRSTATUS2_UARTBTXINT : \
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TX39_INTRSTATUS2_UARTATXINT)
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#define TX39_INTRSTATUS2_UARTTXOVERRUNINT(x) \
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((x) ? TX39_INTRSTATUS2_UARTBTXOVERRUNINT : \
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TX39_INTRSTATUS2_UARTATXOVERRUNINT)
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#define TX39_INTRSTATUS2_UARTEMPTYINT(x) \
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((x) ? TX39_INTRSTATUS2_UARTBEMPTYINT : \
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TX39_INTRSTATUS2_UARTEMPTYINT)
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#define TX39_INTRSTATUS2_UARTDMAFULLINT(x) \
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((x) ? TX39_INTRSTATUS2_UARTBDMAFULLINT : \
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TX39_INTRSTATUS2_UARTADMAFULLINT)
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#define TX39_INTRSTATUS2_UARTDMAHALFINT(x) \
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((x) ? TX39_INTRSTATUS2_UARTBDMAHALFINT : \
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TX39_INTRSTATUS2_UARTADMAHALFINT)
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#ifdef TX391X
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#define TX39_INTRSTATUS2_MBUSTXBUFAVAILINT 0x00000800
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#define TX39_INTRSTATUS2_MBUSTXERRINT 0x00000400
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#define TX39_INTRSTATUS2_MBUSEMPTYINT 0x00000200
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#define TX39_INTRSTATUS2_MBUSRXBUFAVAILINT 0x00000100
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#define TX39_INTRSTATUS2_MBUSRXERRINT 0x00000080
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#define TX39_INTRSTATUS2_MBUSDETINT 0x00000040
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#define TX39_INTRSTATUS2_MBUSDMAFULLINT 0x00000020
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#define TX39_INTRSTATUS2_MBUSDMAHALFINT 0x00000010
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#define TX39_INTRSTATUS2_MBUSPOSINT 0x00000008
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#define TX39_INTRSTATUS2_MBUSNEGINT 0x00000004
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#endif /* TX391X */
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#define TX39_INTRSTATUS2_UARTA 0xffc00000
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#define TX39_INTRSTATUS2_UARTB 0x003ff000
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#ifdef TX391X
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#define TX39_INTRSTATUS2_MBUS 0x00000ffc
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#endif /* TX391X */
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/*
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* Interrupt status/clear 3 register. (Multifunction I/O pin)
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* -> Enable 3 register
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*/
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/* R/W */
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#define TX39_INTRSTATUS3_MFIOPOSINT(r) ((r) << 1)
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#define TX39_INTRSTATUS3_CHIFSPOSINT 0x80000000
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#define TX39_INTRSTATUS3_CHICLKPOSINT 0x40000000
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#define TX39_INTRSTATUS3_CHIDOUTPOSINT 0x20000000
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#define TX39_INTRSTATUS3_CHIDINPOSINT 0x10000000
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#define TX39_INTRSTATUS3_DREQPOSINT 0x08000000
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#define TX39_INTRSTATUS3_DGRINTPOSINT 0x04000000
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#define TX39_INTRSTATUS3_BC32KPOSINT 0x02000000
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#define TX39_INTRSTATUS3_TXDPOSINT 0x01000000
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#define TX39_INTRSTATUS3_RXDPOSINT 0x00800000
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#define TX39_INTRSTATUS3_CS1POSINT 0x00400000
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#define TX39_INTRSTATUS3_CS2POSINT 0x00200000
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#define TX39_INTRSTATUS3_CS3POSINT 0x00100000
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#define TX39_INTRSTATUS3_MCS0POSINT 0x00080000
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#define TX39_INTRSTATUS3_MCS1POSINT 0x00040000
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#define TX39_INTRSTATUS3_MCS2POSINT 0x00020000
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#define TX39_INTRSTATUS3_MCS3POSINT 0x00010000
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#define TX39_INTRSTATUS3_SPICLKPOSINT 0x00008000
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#define TX39_INTRSTATUS3_SPIOUTPOSINT 0x00004000
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#define TX39_INTRSTATUS3_SPINPOSINT 0x00002000
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#define TX39_INTRSTATUS3_SIBMCLKPOSINT 0x00001000
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#define TX39_INTRSTATUS3_CARDREGPOSINT 0x00000800
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#define TX39_INTRSTATUS3_CARDIOWRPOSINT 0x00000400
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#define TX39_INTRSTATUS3_CARDIORDPOSINT 0x00000200
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#define TX39_INTRSTATUS3_CARD1CSLPOSINT 0x00000100
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#define TX39_INTRSTATUS3_CARD1CSHPOSINT 0x00000080
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#define TX39_INTRSTATUS3_CARD2CSLPOSINT 0x00000040
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#define TX39_INTRSTATUS3_CARD2CSHPOSINT 0x00000020
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#define TX39_INTRSTATUS3_CARD1WAITPOSINT 0x00000010
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#define TX39_INTRSTATUS3_CARD2WAITPOSINT 0x00000008
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#define TX39_INTRSTATUS3_CARDDIRPOSINT 0x00000004
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/*
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* Interrupt status/clear 4 register. (Multifunction I/O pin)
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* -> Enable 4 register
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*/
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/* R/W */
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#define TX39_INTRSTATUS4_MFIONEGINT(r) ((r) << 1)
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#define TX39_INTRSTATUS4_CHIFSNEGINT 0x80000000
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#define TX39_INTRSTATUS4_CHICLKNEGINT 0x40000000
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#define TX39_INTRSTATUS4_CHIDOUTNEGINT 0x20000000
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#define TX39_INTRSTATUS4_CHIDINNEGINT 0x10000000
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#define TX39_INTRSTATUS4_DREQNEGINT 0x08000000
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#define TX39_INTRSTATUS4_DGRINTNEGINT 0x04000000
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#define TX39_INTRSTATUS4_BC32KNEGINT 0x02000000
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#define TX39_INTRSTATUS4_TXDNEGINT 0x01000000
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#define TX39_INTRSTATUS4_RXDNEGINT 0x00800000
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#define TX39_INTRSTATUS4_CS1NEGINT 0x00400000
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#define TX39_INTRSTATUS4_CS2NEGINT 0x00200000
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#define TX39_INTRSTATUS4_CS3NEGINT 0x00100000
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#define TX39_INTRSTATUS4_MCS0NEGINT 0x00080000
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#define TX39_INTRSTATUS4_MCS1NEGINT 0x00040000
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#define TX39_INTRSTATUS4_MCS2NEGINT 0x00020000
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#define TX39_INTRSTATUS4_MCS3NEGINT 0x00010000
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#define TX39_INTRSTATUS4_SPICLKNEGINT 0x00008000
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#define TX39_INTRSTATUS4_SPIOUTNEGINT 0x00004000
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#define TX39_INTRSTATUS4_SPINNEGINT 0x00002000
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#define TX39_INTRSTATUS4_SIBMCLKNEGINT 0x00001000
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#define TX39_INTRSTATUS4_CARDREGNEGINT 0x00000800
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#define TX39_INTRSTATUS4_CARDIOWRNEGINT 0x00000400
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#define TX39_INTRSTATUS4_CARDIORDNEGINT 0x00000200
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#define TX39_INTRSTATUS4_CARD1CSLNEGINT 0x00000100
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#define TX39_INTRSTATUS4_CARD1CSHNEGINT 0x00000080
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#define TX39_INTRSTATUS4_CARD2CSLNEGINT 0x00000040
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#define TX39_INTRSTATUS4_CARD2CSHNEGINT 0x00000020
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#define TX39_INTRSTATUS4_CARD1WAITNEGINT 0x00000010
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#define TX39_INTRSTATUS4_CARD2WAITNEGINT 0x00000008
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#define TX39_INTRSTATUS4_CARDDIRNEGINT 0x00000004
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/*
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* Interrupt status/clear 5 register.
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* -> Enable 5 register
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*/
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/* R/W */
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#define TX39_INTRSTATUS5_RTCINT 0x80000000
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#define TX39_INTRSTATUS5_ALARMINT 0x40000000
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#define TX39_INTRSTATUS5_PERINT 0x20000000
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#define TX39_INTRSTATUS5_STPTIMERINT 0x10000000
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#define TX39_INTRSTATUS5_POSPWRINT 0x08000000
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#define TX39_INTRSTATUS5_NEGPWRINT 0x04000000
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#define TX39_INTRSTATUS5_POSPWROKINT 0x02000000
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#define TX39_INTRSTATUS5_NEGPWROKINT 0x01000000
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#define TX39_INTRSTATUS5_POSONBUTNINT 0x00800000
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#define TX39_INTRSTATUS5_NEGONBUTNINT 0x00400000
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#define TX39_INTRSTATUS5_SPIBUFAVAILINT 0x00200000
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#define TX39_INTRSTATUS5_SPIERRINT 0x00100000
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#define TX39_INTRSTATUS5_SPIRCVINT 0x00080000
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#define TX39_INTRSTATUS5_SPIEMPTYINT 0x00040000
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#define TX39_INTRSTATUS5_IRCONSMINT 0x00020000
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#define TX39_INTRSTATUS5_CARSTINT 0x00010000
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#define TX39_INTRSTATUS5_POSCARINT 0x00008000
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#define TX39_INTRSTATUS5_NEGCARINT 0x00004000
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#ifdef TX391X
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#define TX39_INTRSTATUS5_IOPOSINT6 0x00002000
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#define TX39_INTRSTATUS5_IOPOSINT5 0x00001000
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#define TX39_INTRSTATUS5_IOPOSINT4 0x00000800
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#define TX39_INTRSTATUS5_IOPOSINT3 0x00000400
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#define TX39_INTRSTATUS5_IOPOSINT2 0x00000200
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#define TX39_INTRSTATUS5_IOPOSINT1 0x00000100
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#define TX39_INTRSTATUS5_IOPOSINT0 0x00000080
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#define TX39_INTRSTATUS5_IONEGINT6 0x00000040
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#define TX39_INTRSTATUS5_IONEGINT5 0x00000020
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#define TX39_INTRSTATUS5_IONEGINT4 0x00000010
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#define TX39_INTRSTATUS5_IONEGINT3 0x00000008
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#define TX39_INTRSTATUS5_IONEGINT2 0x00000004
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#define TX39_INTRSTATUS5_IONEGINT1 0x00000002
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#define TX39_INTRSTATUS5_IONEGINT0 0x00000001
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#endif /* TX391X */
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#define TX39_INTRSTATUS5_TIMER 0xe0000000
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#define TX39_INTRSTATUS5_POWER 0x1fc00000
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#define TX39_INTRSTATUS5_SPI 0x003c0000
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#define TX39_INTRSTATUS5_IR 0x0003c000
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#ifdef TX391X
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#define TX39_INTRSTATUS5_IO 0x00003fff
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#define TX39_INTRSTATUS5_IOPOSINT_SHIFT 7
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#define TX39_INTRSTATUS5_IOPOSINT_MASK 0x7f
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#define TX39_INTRSTATUS5_IOPOSINT(cr) \
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(((cr) >> TX39_INTRSTATUS5_IOPOSINT_SHIFT) & \
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TX39_INTRSTATUS5_IOPOSINT_MASK)
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#define TX39_INTRSTATUS5_IOPOSINT_SET(cr, val) \
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((cr) | (((val) << TX39_INTRSTATUS5_IOPOSINT_SHIFT) & \
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(TX39_INTRSTATUS5_IOPOSINT_MASK << TX39_INTRSTATUS5_IOPOSINT_SHIFT)))
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#define TX39_INTRSTATUS5_IONEGINT_SHIFT 0
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#define TX39_INTRSTATUS5_IONEGINT_MASK 0x7f
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#define TX39_INTRSTATUS5_IONEGINT(cr) \
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(((cr) >> TX39_INTRSTATUS5_IONEGINT_SHIFT) & \
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TX39_INTRSTATUS5_IONEGINT_MASK)
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#define TX39_INTRSTATUS5_IONEGINT_SET(cr, val) \
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((cr) | (((val) << TX39_INTRSTATUS5_IONEGINT_SHIFT) & \
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(TX39_INTRSTATUS5_IONEGINT_MASK << TX39_INTRSTATUS5_IONEGINT_SHIFT)))
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#endif /* TX391X */
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/*
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* Interrupt status 6 register.
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*/
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/* R */
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#define TX39_INTRSTATUS6_IRQHIGH 0x80000000
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#define TX39_INTRSTATUS6_IRQLOW 0x40000000
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#define TX39_INTRSTATUS6_INTVECT_SHIFT 2
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#define TX39_INTRSTATUS6_INTVECT_MASK 0xf
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#define TX39_INTRSTATUS6_INTVECT(cr) \
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(((cr) >> TX39_INTRSTATUS6_INTVECT_SHIFT) & \
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TX39_INTRSTATUS6_INTVECT_MASK)
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/*
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* Interrupt enable 6 register.
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*/
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/* R/W */
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#define TX39_INTRENABLE6_GLOBALEN 0x00040000
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#define TX39_INTRENABLE6_PRIORITYMASK_SHIFT 0
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#define TX39_INTRENABLE6_PRIORITYMASK_MASK 0xffff
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#define TX39_INTRENABLE6_PRIORITYMASK(cr) \
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(((cr) >> TX39_INTRENABLE6_PRIORITYMASK_SHIFT) & \
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TX39_INTRENABLE6_PRIORITYMASK_MASK)
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#define TX39_INTRENABLE6_PRIORITYMASK_SET(cr, val) \
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((cr) | (((val) << TX39_INTRENABLE6_PRIORITYMASK_SHIFT) & \
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(TX39_INTRENABLE6_PRIORITYMASK_MASK << TX39_INTRENABLE6_PRIORITYMASK_SHIFT)))
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#ifdef TX392X
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/*
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* Interrupt Status 7 Register
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*/
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#define TX3922_INTRSTATUS7_IRTXCINT 0x00100000
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#define TX3922_INTRSTATUS7_IRRXCINT 0x00080000
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#define TX3922_INTRSTATUS7_IRTXEINT 0x00040000
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#define TX3922_INTRSTATUS7_IRRXEINT 0x00020000
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#define TX3922_INTRSTATUS7_IRSIRPXINT 0x00010000
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/*
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* Interrupt Status 8 Register
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*/
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#define TX39_INTRSTATUS8_IOPOSINT15 0x80000000
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#define TX39_INTRSTATUS8_IOPOSINT14 0x40000000
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#define TX39_INTRSTATUS8_IOPOSINT13 0x20000000
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#define TX39_INTRSTATUS8_IOPOSINT12 0x10000000
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#define TX39_INTRSTATUS8_IOPOSINT11 0x08000000
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#define TX39_INTRSTATUS8_IOPOSINT10 0x04000000
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#define TX39_INTRSTATUS8_IOPOSINT9 0x02000000
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#define TX39_INTRSTATUS8_IOPOSINT8 0x01000000
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#define TX39_INTRSTATUS8_IOPOSINT7 0x00800000
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#define TX39_INTRSTATUS8_IOPOSINT6 0x00400000
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#define TX39_INTRSTATUS8_IOPOSINT5 0x00200000
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#define TX39_INTRSTATUS8_IOPOSINT4 0x00100000
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#define TX39_INTRSTATUS8_IOPOSINT3 0x00080000
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#define TX39_INTRSTATUS8_IOPOSINT2 0x00040000
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#define TX39_INTRSTATUS8_IOPOSINT1 0x00020000
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#define TX39_INTRSTATUS8_IOPOSINT0 0x00010000
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#define TX39_INTRSTATUS8_IONEGINT15 0x00008000
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#define TX39_INTRSTATUS8_IONEGINT14 0x00004000
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#define TX39_INTRSTATUS8_IONEGINT13 0x00002000
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#define TX39_INTRSTATUS8_IONEGINT12 0x00001000
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#define TX39_INTRSTATUS8_IONEGINT11 0x00000800
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#define TX39_INTRSTATUS8_IONEGINT10 0x00000400
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#define TX39_INTRSTATUS8_IONEGINT9 0x00000200
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#define TX39_INTRSTATUS8_IONEGINT8 0x00000100
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#define TX39_INTRSTATUS8_IONEGINT7 0x00000080
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#define TX39_INTRSTATUS8_IONEGINT6 0x00000040
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#define TX39_INTRSTATUS8_IONEGINT5 0x00000020
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#define TX39_INTRSTATUS8_IONEGINT4 0x00000010
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#define TX39_INTRSTATUS8_IONEGINT3 0x00000008
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#define TX39_INTRSTATUS8_IONEGINT2 0x00000004
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#define TX39_INTRSTATUS8_IONEGINT1 0x00000002
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#define TX39_INTRSTATUS8_IONEGINT0 0x00000001
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#define TX3922_INTRSTATUS8_IOPOSINT_SHIFT 16
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#define TX3922_INTRSTATUS8_IOPOSINT_MASK 0xffff
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#define TX3922_INTRSTATUS8_IOPOSINT(cr) \
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(((cr) >> TX3922_INTRSTATUS8_IOPOSINT_SHIFT) & \
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TX3922_INTRSTATUS8_IOPOSINT_MASK)
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#define TX3922_INTRSTATUS8_IOPOSINT_SET(cr, val) \
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((cr) | (((val) << TX3922_INTRSTATUS8_IOPOSINT_SHIFT) & \
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(TX3922_INTRSTATUS8_IOPOSINT_MASK << TX3922_INTRSTATUS8_IOPOSINT_SHIFT)))
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#define TX3922_INTRSTATUS8_IONEGINT_SHIFT 0
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#define TX3922_INTRSTATUS8_IONEGINT_MASK 0xffff
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#define TX3922_INTRSTATUS8_IONEGINT(cr) \
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(((cr) >> TX3922_INTRSTATUS8_IONEGINT_SHIFT) & \
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TX3922_INTRSTATUS8_IONEGINT_MASK)
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#define TX3922_INTRSTATUS8_IONEGINT_SET(cr, val) \
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((cr) | (((val) << TX3922_INTRSTATUS8_IONEGINT_SHIFT) & \
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(TX3922_INTRSTATUS8_IONEGINT_MASK << TX3922_INTRSTATUS8_IONEGINT_SHIFT)))
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#endif /* TX392X */
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/*
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* IRQHIGH (Priority level interrupt)
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*/
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#ifdef TX391X
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#define TX39_INTRPRI15_PWROK_BIT 0x00008000
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#define TX39_INTRPRI14_TIMER_ALARM_BIT 0x00004000
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#define TX39_INTRPRI13_TIMER_PERIODIC_BIT 0x00002000
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#define TX39_INTRPRI12_MBUS_BIT 0x00001000
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#define TX39_INTRPRI11_UARTARX_BIT 0x00000800
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#define TX39_INTRPRI10_UARTBRX_BIT 0x00000400
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#define TX39_INTRPRI9_MFIO19_18_17_16POS_BIT 0x00000200
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#define TX39_INTRPRI8_MFIO1_0_IO6_5POS_BIT 0x00000100
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#define TX39_INTRPRI7_MFIO19_18_17_16NEG_BIT 0x00000080
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#define TX39_INTRPRI6_MFIO1_0_IO6_5NEG_BIT 0x00000040
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#define TX39_INTRPRI5_MBUSDMAFULL_BIT 0x00000020
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#define TX39_INTRPRI4_SNDDMACNT_BIT 0x00000010
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#define TX39_INTRPRI3_TELDMACNT_BIT 0x00000008
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#define TX39_INTRPRI2_CHIDMACNT_BIT 0x00000004
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#define TX39_INTRPRI1_IO0POSNEG_BIT 0x00000002
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#define TX39_INTRPRI0_BIT 0x00000001
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#define TX39_INTRPRI15_PWROK 15
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#define TX39_INTRPRI14_TIMER_ALARM 14
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#define TX39_INTRPRI13_TIMER_PERIODIC 13
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#define TX39_INTRPRI12_MBUS 12
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#define TX39_INTRPRI11_UARTARX 11
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#define TX39_INTRPRI10_UARTBRX 10
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#define TX39_INTRPRI9_MFIO19_18_17_16POS 9
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#define TX39_INTRPRI8_MFIO1_0_IO6_5POS 8
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#define TX39_INTRPRI7_MFIO19_18_17_16NEG 7
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#define TX39_INTRPRI6_MFIO1_0_IO6_5NEG 6
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#define TX39_INTRPRI5_MBUSDMAFULL 5
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#define TX39_INTRPRI4_SNDDMACNT 4
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#define TX39_INTRPRI3_TELDMACNT 3
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#define TX39_INTRPRI2_CHIDMACNT 2
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#define TX39_INTRPRI1_IO0POSNEG 1
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#define TX39_INTRPRI0 0
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#endif /* TX391X */
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#ifdef TX392X
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#define TX39_INTRPRI15_PWROK_BIT 0x00008000
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#define TX39_INTRPRI14_TIMER_ALARM_BIT 0x00004000
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#define TX39_INTRPRI13_TIMER_PERIODIC_BIT 0x00002000
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#define TX39_INTRPRI12_UARTABRX_BIT 0x00001000
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#define TX39_INTRPRI11_MFIO19_18_17_16POS_BIT 0x00000800
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#define TX39_INTRPRI10_MFIO1_0_IO6_5POS_BIT 0x00000400
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#define TX39_INTRPRI9_MFIO19_18_17_16NEG_BIT 0x00000200
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#define TX39_INTRPRI8_MFIO1_0_IO6_5NEG_BIT 0x00000100
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#define TX39_INTRPRI5_MBUSDMAFULL_BIT 0x00000020
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#define TX39_INTRPRI4_SNDDMACNT_BIT 0x00000010
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#define TX39_INTRPRI3_TELDMACNT_BIT 0x00000008
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#define TX39_INTRPRI2_CHIDMACNT_BIT 0x00000004
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#define TX39_INTRPRI1_IO0POSNEG_BIT 0x00000002
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#define TX39_INTRPRI0_BIT 0x00000001
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|
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#define TX39_INTRPRI15_PWROK 15
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#define TX39_INTRPRI14_TIMER_ALARM 14
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#define TX39_INTRPRI13_TIMER_PERIODIC 13
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#define TX39_INTRPRI12_UARTABRX 12
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#define TX39_INTRPRI11_MFIO19_18_17_16POS 11
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#define TX39_INTRPRI10_MFIO1_0_IO6_5POS 10
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#define TX39_INTRPRI9_MFIO19_18_17_16NEG 9
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|
#define TX39_INTRPRI8_MFIO1_0_IO6_5NEG 8
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#define TX39_INTRPRI5_IRRXCRXE 5
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|
#define TX39_INTRPRI4_SNDDMACNT 4
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|
#define TX39_INTRPRI3_TELDMACNT 3
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|
#define TX39_INTRPRI2_CHIDMACNT 2
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|
#define TX39_INTRPRI1_IO0POSNEG 1
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|
#define TX39_INTRPRI0 0
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|
#endif /* TX392X */
|
|
|
|
/*
|
|
* CPU connection
|
|
*/
|
|
#define TX39_INTRIRQHIGH_MIPS_HARD_INT 4
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#define TX39_INTRIRQLOW_MIPS_HARD_INT 2
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