129 lines
4.8 KiB
C
129 lines
4.8 KiB
C
/* $NetBSD$ */
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/*-
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* Copyright (c) 2002-2004 Sam Leffler, Errno Consulting, Atheros
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* Communications, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms are permitted
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* provided that the following conditions are met:
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* 1. The materials contained herein are unmodified and are used
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* unmodified.
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* 2. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following NO
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* ''WARRANTY'' disclaimer below (''Disclaimer''), without
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* modification.
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* 3. Redistributions in binary form must reproduce at minimum a
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* disclaimer similar to the Disclaimer below and any redistribution
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* must be conditioned upon including a substantially similar
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* Disclaimer requirement for further binary redistribution.
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* 4. Neither the names of the above-listed copyright holders nor the
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* names of any contributors may be used to endorse or promote
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* product derived from this software without specific prior written
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* permission.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
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* MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
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* FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGES.
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*
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* $Id: ah_osdep.h,v 1.1.1.7 2004/06/09 16:25:50 samleffler Exp $
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*/
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#ifndef _ATH_AH_OSDEP_H_
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#define _ATH_AH_OSDEP_H_
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/*
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* Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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typedef void* HAL_SOFTC;
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typedef bus_space_tag_t HAL_BUS_TAG;
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typedef bus_space_handle_t HAL_BUS_HANDLE;
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typedef bus_addr_t HAL_BUS_ADDR;
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/*
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* Delay n microseconds.
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*/
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extern void ath_hal_delay(int);
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#define OS_DELAY(_n) ath_hal_delay(_n)
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#define OS_MEMZERO(_a, _n) __builtin_memset((_a), 0, (_n))
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#define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
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extern void * ath_hal_memcpy(void *, const void *, size_t);
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#define abs(_a) __builtin_abs(_a)
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struct ath_hal;
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extern u_int32_t ath_hal_getuptime(struct ath_hal *);
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#define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
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/*
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* Byte order/swapping support.
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*/
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#define AH_LITTLE_ENDIAN 1234
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#define AH_BIG_ENDIAN 4321
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/*
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* Register read/write; we assume the registers will always
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* be memory-mapped. Note that register accesses are done
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* using target-specific functions when debugging is enabled
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* (AH_DEBUG) or we are explicitly configured this way. The
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* latter is used on some platforms where the full i/o space
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* cannot be directly mapped.
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*
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* The hardware registers are native little-endian byte order.
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* Big-endian hosts are handled by enabling hardware byte-swap
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* of register reads and writes at reset. But the PCI clock
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* domain registers are not byte swapped! Thus, on big-endian
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* platforms we have to byte-swap thoese registers specifically.
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* Most of this code is collapsed at compile time because the
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* register values are constants.
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*/
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#if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
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/* use functions to do register operations */
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#define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
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#define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
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extern void ath_hal_reg_write(struct ath_hal *ah,
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u_int reg, u_int32_t val);
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extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
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#else
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/* inline register operations */
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#if AH_BYTE_ORDER == AH_BIG_ENDIAN
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#define OS_REG_WRITE(_ah, _reg, _val) do { \
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if ( (_reg) >= 0x4000 && (_reg) < 0x5000) \
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bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
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(_reg), htole32(_val)); \
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else \
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bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, \
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(_reg), (_val)); \
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} while (0)
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#define OS_REG_READ(_ah, _reg) \
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(((_reg) >= 0x4000 && (_reg) < 0x5000) ? \
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le32toh(bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, \
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(_reg))) : \
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bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
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#else /* AH_LITTLE_ENDIAN */
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#define OS_REG_WRITE(_ah, _reg, _val) \
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bus_space_write_4((_ah)->ah_st, (_ah)->ah_sh, (_reg), (_val))
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#define OS_REG_READ(_ah, _reg) \
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((u_int32_t) bus_space_read_4((_ah)->ah_st, (_ah)->ah_sh, (_reg)))
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#endif /* AH_BYTE_ORDER */
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#endif /* AH_DEBUG || AH_REGFUNC */
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#define OS_MARK(_ah, _id, _v)
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extern void ath_hal_detach(struct ath_hal *);
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#endif /* _ATH_AH_OSDEP_H_ */
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