477 lines
14 KiB
C
477 lines
14 KiB
C
/* $NetBSD: asc_ioasic.c,v 1.10 2000/09/28 03:27:29 mhitch Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Tohru Nishimura.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: asc_ioasic.c,v 1.10 2000/09/28 03:27:29 mhitch Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/bus.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <dev/tc/tcvar.h>
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#include <dev/tc/ioasicvar.h>
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#include <dev/tc/ioasicreg.h>
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struct asc_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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bus_space_tag_t sc_bst; /* bus space tag */
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bus_space_handle_t sc_bsh; /* bus space handle */
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bus_space_handle_t sc_scsi_bsh; /* ASC register handle */
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bus_dma_tag_t sc_dmat; /* bus dma tag */
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bus_dmamap_t sc_dmamap; /* bus dmamap */
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caddr_t *sc_dmaaddr;
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size_t *sc_dmalen;
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size_t sc_dmasize;
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unsigned sc_flags;
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#define ASC_ISPULLUP 0x0001
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#define ASC_DMAACTIVE 0x0002
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#define ASC_MAPLOADED 0x0004
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};
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static int asc_ioasic_match __P((struct device *, struct cfdata *, void *));
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static void asc_ioasic_attach __P((struct device *, struct device *, void *));
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struct cfattach xasc_ioasic_ca = {
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sizeof(struct asc_softc), asc_ioasic_match, asc_ioasic_attach
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};
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static u_char asc_read_reg __P((struct ncr53c9x_softc *, int));
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static void asc_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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static int asc_dma_isintr __P((struct ncr53c9x_softc *sc));
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static void asc_ioasic_reset __P((struct ncr53c9x_softc *));
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static int asc_ioasic_intr __P((struct ncr53c9x_softc *));
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static int asc_ioasic_setup __P((struct ncr53c9x_softc *,
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caddr_t *, size_t *, int, size_t *));
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static void asc_ioasic_go __P((struct ncr53c9x_softc *));
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static void asc_ioasic_stop __P((struct ncr53c9x_softc *));
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static int asc_dma_isactive __P((struct ncr53c9x_softc *));
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static void asc_clear_latched_intr __P((struct ncr53c9x_softc *));
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static struct ncr53c9x_glue asc_ioasic_glue = {
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asc_read_reg,
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asc_write_reg,
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asc_dma_isintr,
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asc_ioasic_reset,
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asc_ioasic_intr,
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asc_ioasic_setup,
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asc_ioasic_go,
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asc_ioasic_stop,
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asc_dma_isactive,
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asc_clear_latched_intr,
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};
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static int
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asc_ioasic_match(parent, cfdata, aux)
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struct device *parent;
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struct cfdata *cfdata;
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void *aux;
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{
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struct ioasicdev_attach_args *d = aux;
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if (strncmp("asc", d->iada_modname, TC_ROM_LLEN))
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return 0;
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return 1;
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}
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static void
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asc_ioasic_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct ioasicdev_attach_args *d = aux;
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struct asc_softc *asc = (struct asc_softc *)self;
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struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x;
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &asc_ioasic_glue;
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asc->sc_bst = ((struct ioasic_softc *)parent)->sc_bst;
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asc->sc_bsh = ((struct ioasic_softc *)parent)->sc_bsh;
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if (bus_space_subregion(asc->sc_bst, asc->sc_bsh,
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IOASIC_SLOT_12_START, 0x100, &asc->sc_scsi_bsh)) {
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printf(": failed to map device registers\n");
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return;
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}
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asc->sc_dmat = ((struct ioasic_softc *)parent)->sc_dmat;
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if (bus_dmamap_create(asc->sc_dmat, NBPG * 2,
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2, NBPG, NBPG, BUS_DMA_NOWAIT, &asc->sc_dmamap)) {
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printf(": failed to create DMA map\n");
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return;
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}
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sc->sc_id = 7;
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sc->sc_freq = 25000000;
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/* gimme Mhz */
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sc->sc_freq /= 1000000;
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ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_BIO,
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ncr53c9x_intr, sc);
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* Set up static configuration info.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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sc->sc_cfg3 = 0;
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sc->sc_rev = NCR_VARIANT_NCR53C94;
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/*
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* XXX minsync and maxxfer _should_ be set up in MI code,
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* XXX but it appears to have some dependency on what sort
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* XXX of DMA we're hooked up to, etc.
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*/
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4 ;
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sc->sc_maxxfer = 64 * 1024;
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/* Do the common parts of attachment. */
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ncr53c9x_attach(sc, NULL, NULL);
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}
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void
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asc_ioasic_reset(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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u_int32_t ssr;
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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ssr &= ~IOASIC_CSR_DMAEN_SCSI;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, 0);
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if (asc->sc_flags & ASC_MAPLOADED)
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bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
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asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED);
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}
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#define TWOPAGE(a) (NBPG*2 - ((a) & (NBPG-1)))
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int
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asc_ioasic_setup(sc, addr, len, ispullup, dmasize)
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struct ncr53c9x_softc *sc;
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caddr_t *addr;
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size_t *len;
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int ispullup;
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size_t *dmasize;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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u_int32_t ssr, scr, *p;
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size_t size;
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vaddr_t cp;
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NCR_DMA(("%s: start %d@%p,%s\n", sc->sc_dev.dv_xname,
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*asc->sc_dmalen, *asc->sc_dmaaddr, ispullup ? "IN" : "OUT"));
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/* upto two 4KB pages */
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size = min(*dmasize, TWOPAGE((size_t)*addr));
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asc->sc_dmaaddr = addr;
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asc->sc_dmalen = len;
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asc->sc_dmasize = size;
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asc->sc_flags = (ispullup) ? ASC_ISPULLUP : 0;
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*dmasize = size; /* return trimmed transfer size */
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/* stop DMA engine first */
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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ssr &= ~IOASIC_CSR_DMAEN_SCSI;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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/* have dmamap for the transfering addresses */
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if (bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap,
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*addr, size,
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NULL /* kernel address */, BUS_DMA_NOWAIT))
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panic("%s: cannot allocate DMA address", sc->sc_dev.dv_xname);
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/* take care of 8B constraint on starting address */
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cp = (vaddr_t)*addr;
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if ((cp & 7) == 0) {
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/* comfortably aligned to 8B boundary */
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scr = 0;
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}
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else {
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/* truncate to the boundary */
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p = (u_int32_t *)(cp & ~7);
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/* how many 16bit quantities in subject */
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scr = (cp & 7) >> 1;
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/* trim down physical address too */
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asc->sc_dmamap->dm_segs[0].ds_addr &= ~7;
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asc->sc_dmamap->dm_segs[0].ds_len += (cp & 6);
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if ((asc->sc_flags & ASC_ISPULLUP) == 0) {
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/* push down to SCSI device */
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scr |= 4;
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/* round up physical address in this case */
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asc->sc_dmamap->dm_segs[0].ds_addr += 8;
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/* don't care excess cache flush */
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}
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/* pack fixup data in SDR0/SDR1 pair and instruct SCR */
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_SDR0, p[0]);
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_SDR1, p[1]);
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}
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_DMAPTR,
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IOASIC_DMA_ADDR(asc->sc_dmamap->dm_segs[0].ds_addr));
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bus_space_write_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_NEXTPTR,
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(asc->sc_dmamap->dm_nsegs == 1)
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? ~0 : IOASIC_DMA_ADDR(asc->sc_dmamap->dm_segs[1].ds_addr));
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR, scr);
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/* synchronize dmamap contents with memory image */
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bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
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0, size,
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(ispullup) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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asc->sc_flags |= ASC_MAPLOADED;
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return 0;
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}
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void
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asc_ioasic_go(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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u_int32_t ssr;
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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if (asc->sc_flags & ASC_ISPULLUP)
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ssr |= IOASIC_CSR_SCSI_DIR;
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else {
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/* ULTRIX does in this way */
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ssr &= ~IOASIC_CSR_SCSI_DIR;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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}
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ssr |= IOASIC_CSR_DMAEN_SCSI;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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asc->sc_flags |= ASC_DMAACTIVE;
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}
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static int
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asc_ioasic_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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int trans, resid;
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u_int tcl, tcm, ssr, scr, intr;
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if ((asc->sc_flags & ASC_DMAACTIVE) == 0)
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panic("ioasic_intr: DMA wasn't active");
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#define IOASIC_ASC_ERRORS \
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(IOASIC_INTR_SCSI_PTR_LOAD|IOASIC_INTR_SCSI_OVRUN|IOASIC_INTR_SCSI_READ_E)
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/*
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* When doing polled I/O, the SCSI bits in the interrupt register won't
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* get cleared by the interrupt processing. This will cause the DMA
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* address registers to not load on the next DMA transfer.
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* Check for these bits here, and clear them if needed.
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*/
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intr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR);
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if ((intr & IOASIC_ASC_ERRORS) != 0) {
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intr &= ~IOASIC_ASC_ERRORS;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_INTR, intr);
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}
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/* DMA has stopped */
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ssr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR);
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ssr &= ~IOASIC_CSR_DMAEN_SCSI;
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bus_space_write_4(asc->sc_bst, asc->sc_bsh, IOASIC_CSR, ssr);
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asc->sc_flags &= ~ASC_DMAACTIVE;
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if (asc->sc_dmasize == 0) {
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/* A "Transfer Pad" operation completed */
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tcl = NCR_READ_REG(sc, NCR_TCL);
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tcm = NCR_READ_REG(sc, NCR_TCM);
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NCR_DMA(("ioasic_intr: discarded %d bytes (tcl=%d, tcm=%d)\n",
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tcl | (tcm << 8), tcl, tcm));
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return 0;
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}
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resid = 0;
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if ((asc->sc_flags & ASC_ISPULLUP) == 0 &&
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(resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
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NCR_DMA(("ioasic_intr: empty FIFO of %d ", resid));
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DELAY(1);
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}
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resid += (tcl = NCR_READ_REG(sc, NCR_TCL));
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resid += (tcm = NCR_READ_REG(sc, NCR_TCM)) << 8;
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trans = asc->sc_dmasize - resid;
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if (trans < 0) { /* transferred < 0 ? */
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printf("ioasic_intr: xfer (%d) > req (%d)\n",
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trans, asc->sc_dmasize);
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trans = asc->sc_dmasize;
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}
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NCR_DMA(("ioasic_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n",
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tcl, tcm, trans, resid));
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bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
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0, asc->sc_dmasize,
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(asc->sc_flags & ASC_ISPULLUP)
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? BUS_DMASYNC_POSTREAD
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: BUS_DMASYNC_POSTWRITE);
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scr = bus_space_read_4(asc->sc_bst, asc->sc_bsh, IOASIC_SCSI_SCR);
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if ((asc->sc_flags & ASC_ISPULLUP) && scr != 0) {
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u_int32_t sdr[2], ptr;
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sdr[0] = bus_space_read_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_SDR0);
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sdr[1] = bus_space_read_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_SDR1);
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ptr = bus_space_read_4(asc->sc_bst, asc->sc_bsh,
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IOASIC_SCSI_DMAPTR);
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ptr = (ptr >> 3) & 0x1ffffffc;
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/*
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* scr: 1 -> short[0]
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* 2 -> short[0] + short[1]
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* 3 -> short[0] + short[1] + short[2]
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*/
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scr &= IOASIC_SCR_WORD;
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memcpy((void *)MIPS_PHYS_TO_KSEG0(ptr), sdr, scr << 1);
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}
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bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
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asc->sc_flags &= ~ASC_MAPLOADED;
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*asc->sc_dmalen -= trans;
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*asc->sc_dmaaddr += trans;
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return 0;
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}
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void
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asc_ioasic_stop(sc)
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struct ncr53c9x_softc *sc;
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{
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struct asc_softc *asc = (struct asc_softc *)sc;
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if (asc->sc_flags & ASC_MAPLOADED) {
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bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap,
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0, asc->sc_dmasize,
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(asc->sc_flags & ASC_ISPULLUP)
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? BUS_DMASYNC_POSTREAD
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: BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap);
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}
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asc->sc_flags &= ~(ASC_DMAACTIVE|ASC_MAPLOADED);
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}
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static u_char
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asc_read_reg(sc, reg)
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struct ncr53c9x_softc *sc;
|
|
int reg;
|
|
{
|
|
struct asc_softc *asc = (struct asc_softc *)sc;
|
|
u_int32_t v;
|
|
|
|
v = bus_space_read_4(asc->sc_bst,
|
|
asc->sc_scsi_bsh, reg * sizeof(u_int32_t));
|
|
|
|
return v & 0xff;
|
|
}
|
|
|
|
static void
|
|
asc_write_reg(sc, reg, val)
|
|
struct ncr53c9x_softc *sc;
|
|
int reg;
|
|
u_char val;
|
|
{
|
|
struct asc_softc *asc = (struct asc_softc *)sc;
|
|
|
|
bus_space_write_4(asc->sc_bst,
|
|
asc->sc_scsi_bsh, reg * sizeof(u_int32_t), val);
|
|
}
|
|
|
|
static int
|
|
asc_dma_isintr(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
return !!(NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT);
|
|
}
|
|
|
|
static int
|
|
asc_dma_isactive(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
struct asc_softc *asc = (struct asc_softc *)sc;
|
|
|
|
return !!(asc->sc_flags & ASC_DMAACTIVE);
|
|
}
|
|
|
|
static void
|
|
asc_clear_latched_intr(sc)
|
|
struct ncr53c9x_softc *sc;
|
|
{
|
|
}
|