70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
/* $NetBSD: exynos_intr.h,v 1.2 2014/09/05 08:01:05 skrll Exp $ */
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/*-
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* Copyright (c) 2014 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Nick Hudson
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_SAMSUNG_EXYNOS_INTR_H_
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#define _ARM_SAMSUNG_EXYNOS_INTR_H_
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#define PIC_MAXSOURCES GIC_MAXSOURCES(224)
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#define PIC_MAXMAXSOURCES (PIC_MAXSOURCES + 32) /* XXX */
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/*
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* The Exynos uses a generic interrupt controller
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*/
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#include <arm/cortex/gic_intr.h>
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#ifdef _KERNEL_OPT
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#include "opt_exynos.h"
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#endif
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/*
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* The GIC supports
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* - 16 Software Generated Interrupts (SGIs)
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* - 16 Private Peripheral Interrupts (PPIs)
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* - 127 Shared Peripheral Interrupts (SPIs)
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*/
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#define EXYNOS_NSPI 128
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#define EXYNOS_COMBINERBASE EXYNOS_SPIBASE + EXYNOS_NSPI
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#define EXYNOS_BITSPERGROUP 8
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#define EXYNOS_COMBINERIRQ(g, b) \
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(EXYNOS_COMBINERBASE + ((g) * EXYNOS_BITSPERGROUP + (b)))
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#define IRQ_MCT_LTIMER IRQ_PPI(12)
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#ifdef EXYNOS5
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#include <arm/cortex/gtmr_intr.h>
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#endif
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#endif /* _ARM_SAMSUNG_EXYNOS_INTR_H_ */
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