177 lines
6.7 KiB
C
177 lines
6.7 KiB
C
/* $NetBSD: sccreg.h,v 1.3 1997/04/06 22:30:30 cgd Exp $ */
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/*
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* Copyright (c) 1991,1990,1989,1994,1995 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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/*-
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)sccreg.h 8.1 (Berkeley) 6/10/93
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*/
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/*
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* Definitions for Intel 82530 serial communications chip. Each chip is a
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* dual uart with the A channels used for the keyboard and mouse with the B
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* channel(s) for comm ports with modem control. Since some registers are
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* used for the other channel, the following macros are used to access the
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* register ports.
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*
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* Actual access to the registers is provided by sccvar.h, as it's
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* machine-dependent.
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*/
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/* Scc channel numbers; B channel comes first. */
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#define SCC_CHANNEL_B 0
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#define SCC_CHANNEL_A 1
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#define SCC_INIT_REG(scc, chan) { \
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char tmp; \
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scc_get_datum((scc)->scc_channel[(chan)].scc_command, tmp); \
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scc_get_datum((scc)->scc_channel[(chan)].scc_command, tmp); \
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}
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#define SCC_READ_REG(scc, chan, reg, val) { \
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scc_set_datum((scc)->scc_channel[(chan)].scc_command, reg); \
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scc_get_datum((scc)->scc_channel[(chan)].scc_command, val); \
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}
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#define SCC_READ_REG_ZERO(scc, chan, val) { \
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scc_get_datum((scc)->scc_channel[(chan)].scc_command, val); \
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}
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#define SCC_WRITE_REG(scc, chan, reg, val) { \
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scc_set_datum((scc)->scc_channel[(chan)].scc_command, reg); \
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scc_set_datum((scc)->scc_channel[(chan)].scc_command, val); \
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}
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#define SCC_WRITE_REG_ZERO(scc, chan, val) { \
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scc_set_datum((scc)->scc_channel[(chan)].scc_command, val); \
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}
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#define SCC_READ_DATA(scc, chan, val) { \
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scc_get_datum((scc)->scc_channel[(chan)].scc_data, val); \
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}
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#define SCC_WRITE_DATA(scc, chan, val) { \
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scc_set_datum((scc)->scc_channel[(chan)].scc_data, val); \
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}
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/* Addressable registers. */
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#define SCC_RR0 0 /* status register */
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#define SCC_RR1 1 /* special receive conditions */
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#define SCC_RR8 8 /* recv buffer (alias for data) */
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#define SCC_RR10 10 /* sdlc status */
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#define SCC_RR15 15 /* interrupts currently enabled */
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#define SCC_WR0 0 /* reg select, and commands */
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#define SCC_WR1 1 /* interrupt and DMA enables */
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#define SCC_WR3 3 /* receiver params and enables */
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#define SCC_WR4 4 /* clock/char/parity params */
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#define SCC_WR5 5 /* xmit params and enables */
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#define SCC_WR8 8 /* xmit buffer (alias for data) */
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#define SCC_WR9 9 /* vectoring and resets */
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#define SCC_WR10 10 /* synchr params */
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#define SCC_WR11 11 /* clocking definitions */
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#define SCC_WR14 14 /* BRG enables and commands */
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#define SCC_WR15 15 /* interrupt enables */
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/* Read register's defines. */
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/*
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* RR2 contains the interrupt vector unmodified (channel A) or
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* modified as follows (channel B, if vector-include-status).
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*/
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#define SCC_RR2_STATUS(val) ((val)&0xf)
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#define SCC_RR2_B_XMIT_DONE 0x0
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#define SCC_RR2_B_EXT_STATUS 0x2
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#define SCC_RR2_B_RECV_DONE 0x4
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#define SCC_RR2_B_RECV_SPECIAL 0x6
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#define SCC_RR2_A_XMIT_DONE 0x8
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#define SCC_RR2_A_EXT_STATUS 0xa
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#define SCC_RR2_A_RECV_DONE 0xc
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#define SCC_RR2_A_RECV_SPECIAL 0xe
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/* RR12/RR13 hold the timing base, upper byte in RR13. */
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#define SCC_GET_TIMING_BASE(scc, chan, val) { \
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register char tmp; \
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SCC_READ_REG(scc, chan, ZSRR_BAUDLO, val); \
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SCC_READ_REG(scc, chan, ZSRR_BAUDHI, tmp); \
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(val) = ((val) << 8) | (tmp & 0xff); \
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}
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/*
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* Write register's defines.
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*/
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/* WR12/WR13 are for timing base preset */
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#define SCC_SET_TIMING_BASE(scc, chan, val) { \
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SCC_WRITE_REG(scc, chan, ZSWR_BAUDLO, val); \
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SCC_WRITE_REG(scc, chan, ZSWR_BAUDHI, (val) >> 8); \
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}
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/* Bits in dm lsr, copied from dmreg.h. */
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#define DML_DSR 0000400 /* data set ready, not a real DM bit */
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#define DML_RNG 0000200 /* ring */
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#define DML_CAR 0000100 /* carrier detect */
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#define DML_CTS 0000040 /* clear to send */
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#define DML_SR 0000020 /* secondary receive */
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#define DML_ST 0000010 /* secondary transmit */
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#define DML_RTS 0000004 /* request to send */
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#define DML_DTR 0000002 /* data terminal ready */
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#define DML_LE 0000001 /* line enable */
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