159 lines
4.4 KiB
C++
159 lines
4.4 KiB
C++
/* -*-C++-*- $NetBSD: mips_arch.cpp,v 1.1 2001/02/09 18:35:05 uch Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#undef DEBUG_KERNADDR_ACCESS
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#undef DEBUG_CP0_ACCESS
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#include <hpcboot.h>
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#include <mips/mips_arch.h>
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#include <console.h>
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#include <memory.h>
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MIPSArchitecture::MIPSArchitecture(Console *&cons, MemoryManager *&mem)
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: Architecture(cons, mem)
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{
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/* NO-OP */
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}
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MIPSArchitecture::~MIPSArchitecture(void)
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{
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/* NO-OP */
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}
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void
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MIPSArchitecture::systemInfo()
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{
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u_int32_t r0, r1;
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Architecture::systemInfo();
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r0 = r1 = 0;
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#ifdef DEBUG_CP0_ACCESS
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/* CP0 access test */
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_kmode = SetKMode(1);
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DPRINTF((TEXT("status register test\n")));
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GET_SR(r0);
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DPRINTF((TEXT("current value: 0x%08x\n"), r0));
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SET_SR(r1);
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GET_SR(r1);
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DPRINTF((TEXT("write test: 0x%08x\n"), r1));
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SET_SR(r0);
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SetKMode(_kmode);
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#endif // DEBUG_CP0_ACCESS
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}
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BOOL
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MIPSArchitecture::init()
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{
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if (!_mem->init()) {
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DPRINTF((TEXT("can't initialize memory manager.\n")));
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return FALSE;
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}
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return TRUE;
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}
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BOOL
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MIPSArchitecture::setupLoader()
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{
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vaddr_t v;
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#ifdef DEBUG_KERNADDR_ACCESS // kernel address access test
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#define TEST_MAGIC 0xac1dcafe
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paddr_t p;
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u_int32_t r0;
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_kmode = SetKMode(1);
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_mem->getPage(v, p);
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VOLATILE_REF(ptokv(p)) = TEST_MAGIC;
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cacheFlush();
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r0 = VOLATILE_REF(v);
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DPRINTF((TEXT("kernel address access test: %S\n"),
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r0 == TEST_MAGIC ? "OK" : "NG"));
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SetKMode(_kmode);
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#endif // DEBUG_KERNADDR_ACCESS
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if (!_mem->getPage(v , _loader_addr)) {
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DPRINTF((TEXT("can't get page for 2nd loader.\n")));
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return FALSE;
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}
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DPRINTF((TEXT("2nd bootloader vaddr=0x%08x paddr=0x%08x\n"),
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(unsigned)v,(unsigned)_loader_addr));
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memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize());
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DPRINTF((TEXT("2nd bootloader copy done.\n")));
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return TRUE;
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}
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void
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MIPSArchitecture::jump(paddr_t info, paddr_t pvec)
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{
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kaddr_t sp;
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vaddr_t v;
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paddr_t p;
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// stack for bootloader(but mips loader don't use stack)
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_mem->getPage(v, p);
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sp = ptokv(p + _mem->getPageSize() - 0x10);
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info = ptokv(info);
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pvec = ptokv(pvec);
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_loader_addr = ptokv(_loader_addr);
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// switch kernel mode.
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SetKMode(1);
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if (SetKMode(1) != 1) {
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DPRINTF((TEXT("SetKMode(1) failed.\n")));
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return;
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}
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DPRINTF((TEXT("jump to 0x%08x(info=0x%08x, pvec=0x%08x\n"),
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_loader_addr, info, pvec));
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// writeback whole D-cache and invalidate whole I-cache.
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// 2nd boot-loader access data via kseg0 which were writed via kuseg,
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cacheFlush();
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// jump to 2nd-loader(run kseg0)
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__asm(".set noreorder;"
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"jr a3;"
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"move sp, a2;"
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".set reorder", info, pvec, sp, _loader_addr);
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// NOTREACHED
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}
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