131 lines
3.4 KiB
Plaintext
131 lines
3.4 KiB
Plaintext
# $NetBSD: CAYMAN,v 1.5 2002/08/30 11:25:09 scw Exp $
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#
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# Config file for SuperH "CAYMAN" SH-5 Evaluation board
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#
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include "arch/evbsh5/conf/std.evbsh5.el"
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maxusers 2
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options INCLUDE_CONFIG_FILE
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#ident "CAYMAN-$Revision: 1.5 $"
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# Uncomment this to build a 64-bit kernel
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#makeoptions SH5_ABI=64
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makeoptions DEFCOPTS="-g"
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makeoptions DEBUG="-g"
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options DIAGNOSTIC
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options DEBUG
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options DDB
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options KTRACE # system call tracing via ktrace(1)
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options SYSTRACE # system call vetting via systrace(1)
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file-system FFS
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file-system NFS
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file-system KERNFS
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file-system MFS
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options SOFTDEP
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options INET
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#options INET6
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config netbsd root on ? type ?
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options NFS_BOOT_DHCP
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pseudo-device loop
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pseudo-device bpfilter
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pseudo-device pty
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pseudo-device rnd
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# The mainbus to which all devices attach
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mainbus0 at root
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#
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# The SuperHyway bus is the main interconnect between the constituent
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# "modules" which make up an SH-5 system
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#
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superhyway0 at mainbus0
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#
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# These are the "modules" present on the Cayman's SH-5
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#
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cpu0 at superhyway0 pport 0x0d # A single CPU
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#emi0 at superhyway0 pport 0x80 # The memory controller module
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pbridge0 at superhyway0 pport 0x09 # Peripheral Bridge
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#dmac0 at superhyway0 pport 0x0e # DMA controller
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femi0 at superhyway0 pport 0x08 # Flash/External memory
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#pchb0 at superhyway0 pport 0x60 # PCI bus
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#
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# The Peripheral Bridge and all its sub-devices are actually on the same
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# silicon as the CPU itself.
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#
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cprc0 at pbridge0 # Clock, Power & Reset Control
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intc0 at pbridge0 # Interrupt controller
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options SH5_INTC_IRL_MODE_INDEP # Independent IRL[0-3] inputs
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tmu0 at pbridge0 ipl 14 intevt 0x400 # Timer
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scif0 at pbridge0 ipl 12 intevt 0x700 # On-chip serial controller
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rtc0 at pbridge0 # Battery-backed Date/Time chip
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#
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# The Clock, Power and Reset controller has a number of sub-devices, only one
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# of which is currently used.
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#
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clock0 at cprc0 # Primary clock generator
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#watchdog0 at cprc0 # Watchdog
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#power0 at cprc0 # Power Management
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#reset0 at cprc0 # Reset controller
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#
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# The FEMI module (which hangs off the SuperHyway) is actually more than
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# just an interface to Flash memory. It's pretty much a complete expansion
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# bus in its own right.
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#
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sysfpga0 at femi0 offset 0x4000000 # The main System FPGA chip
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#
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# The Super I/O chip is straight out of the x86 PeeCee world in that
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# it implements a bunch if "standard" PeeCee type devices (although
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# a few of those are not connected on Cayman).
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#
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# We make it look like a PeeCee isa bus so that we can re-use all the
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# pre-existing NetBSD drivers for the devices implemented in the Super IO.
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#
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superio0 at sysfpga0 # SMC Super I/O Device
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isa0 at superio0 # The ISAbus attachment.
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sm0 at superio0 offset 0x1000 irq 10 # SMC91C100 LAN controller
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#
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# These are the devices Cayman uses
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#
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# Note that the addresses and irqs are hard-coded and should really be
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# moved into a `knowndevs' structure ...
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#
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#pckbc0 at isa0 # Keyboard Controller
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#pms0 at pckbc0 # Mouse
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com0 at isa0 port 0x3f8 irq 4 # PC-style serial ports
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com1 at isa0 port 0x2f8 irq 3
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lpt0 at isa0 port 0x378 irq 7 # Parallel printer port
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#wdc0 at isa0 port 0x1f0 irq 14 flags 0x0 # IDE-style disk controller
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# Support for IDE/ATAPI device
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#wd* at wdc0 channel ? drive ? flags 0x0000
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#atapibus* at wdc0 channel ?
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#cd* at atapibus? drive ? flags 0x0000
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# The MII device on the LAN controller
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sqphy* at mii? phy ?
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#
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# The DTF debug interface.
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#
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#dtfcons0 at mainbus0
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