96 lines
4.0 KiB
C
96 lines
4.0 KiB
C
/* $NetBSD: i8259reg.h,v 1.4 2008/04/28 20:23:50 martin Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_I8259REG_H_
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#define _DEV_IC_I8259REG_H_
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/*
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* Register definitions for the Intel i8259 Programmable Interrupt
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* Controller.
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*
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* XXX More bits should be filled in, here, as this was taken from
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* XXX the Intel PIIX4 manual. Someone with a real 8259 data sheet
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* XXX should fill them in.
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*/
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/*
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* Note a write to ICW1 starts an initialization cycle, and must be
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* followied by writes to ICW2, ICW3, and ICW4.
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*/
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#define PIC_ICW1 0x00 /* Initialization Command Word 1 (w) */
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#define ICW1_IC4 (1U << 0) /* ICW4 Write Required */
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#define ICW1_SNGL (1U << 1) /* 1 == single, 0 == cascade */
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#define ICW1_ADI (1U << 2) /* CALL address interval */
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#define ICW1_LTIM (1U << 3) /* 1 == intrs are level trigger */
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#define ICW1_SELECT (1U << 4) /* select ICW1 */
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#define ICW1_IVA(x) ((x) << 5) /* interrupt vector address (MCS-80) */
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#define PIC_ICW2 0x01 /* Initialization Command Word 2 (w) */
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#define ICW2_VECTOR(x) ((x) & 0xf8) /* vector base address */
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#define ICW2_IRL(x) ((x) << 0) /* interrupt request level */
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#define PIC_ICW3 0x01 /* Initialization Command Word 3 (w) */
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#define ICW3_CASCADE(x) (1U << (x)) /* cascaded mode enable */
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#define ICW3_SIC(x) ((x) << 0) /* slave identifcation code */
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#define PIC_ICW4 0x01 /* Initialization Command Word 4 (w) */
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#define ICW4_8086 (1U << 0) /* 8086 mode */
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#define ICW4_AEOI (1U << 1) /* automatic end-of-interrupt */
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#define ICW4_BUFM (1U << 2) /* buffered mode master */
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#define ICW4_BUF (1U << 3) /* buffered mode */
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#define ICW4_SFNM (1U << 4) /* special fully nested mode */
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/*
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* After an initialization sequence, you get to access the OCWs.
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*/
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#define PIC_OCW1 0x01 /* Operational Control Word 1 (r/w) */
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#define OCW1_IRM(x) (1U << (x)) /* interrupt request mask */
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#define PIC_OCW2 0x00 /* Operational Control Word 2 (w) */
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#define OCW2_SELECT (0) /* select OCW2 */
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#define OCW2_EOI (1U << 5) /* EOI */
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#define OCW2_SL (1U << 6) /* specific */
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#define OCW2_R (1U << 7) /* rotate */
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#define OCW2_ILS(x) ((x) << 0) /* interrupt level select */
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#define PIC_OCW3 0x00 /* Operational Control Word 3 (r/w) */
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#define OCW3_SSMM (1U << 6) /* set special mask mode */
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#define OCW3_SMM (1U << 5) /* 1 = enable smm, 0 = disable */
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#define OCW3_SELECT (1U << 3) /* select OCW3 */
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#define OCW3_POLL (1U << 2) /* poll mode command */
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#define OCW3_RR (1U << 1) /* register read */
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#define OCW3_RIS (1U << 0) /* 1 = read IS, 0 = read IR */
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#define OCW3_POLL_IRQ(x) ((x) & 0x7f)
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#define OCW3_POLL_PENDING (1U << 7)
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#endif /* _DEV_IC_I8259REG_H_ */
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