9b4c0e34d2
x86-64. Since there's no hardware available yet, this port is only known to run on the Simics simulator for at the moment, and as such uses the PC devices that it simulates for now. It will be developed more (and cleaned up) as the hardware becomes available.
136 lines
4.8 KiB
C
136 lines
4.8 KiB
C
/* $NetBSD: pte.h,v 1.1 2001/06/19 00:20:12 fvdl Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Frank van der Linden for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _X86_64_PTE_H_
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#define _X86_64_PTE_H_
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/*
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* x86-64 MMU hardware structure:
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*
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* the (first generation) x86-64 MMU is a 4-level MMU which maps 2^48 bytes
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* of virtual memory. The pagesize we use is is 4K (4096 [0x1000] bytes),
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* although 2M and 4M can be used as well. The indexes in the levels
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* are 9 bits wide (512 64bit entries per level), dividing the bits
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* 9-9-9-9-12.
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*
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* The top level table, called PML4, contains 512 64bit entries pointing
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* to 3rd level table. The 3rd level table is called the 'page directory
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* pointers directory' and has 512 entries pointing to page directories.
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* The 2nd level is the page directory, containing 512 pointers to
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* page table pages. Lastly, level 1 consists of pages containing 512
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* PTEs.
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*
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* Simply put, levels 4-1 all consist of pages containing 512
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* entries pointing to the next level. Level 0 is the actual PTEs
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* themselves.
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*
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* For a description on the other bits, which are i386 compatible,
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* see the i386 pte.h
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*/
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#if !defined(_LOCORE)
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/*
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* here we define the data types for PDEs and PTEs
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*/
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typedef u_int64_t pd_entry_t; /* PDE */
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typedef u_int64_t pt_entry_t; /* PTE */
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#endif
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/*
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* now we define various for playing with virtual addresses
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*/
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#define L1_SHIFT 12
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#define L2_SHIFT 21
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#define L3_SHIFT 30
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#define L4_SHIFT 39
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#define NBPD_L1 (1ULL << L1_SHIFT) /* # bytes mapped by L1 ent (4K) */
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#define NBPD_L2 (1ULL << L2_SHIFT) /* # bytes mapped by L2 ent (2MB) */
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#define NBPD_L3 (1ULL << L3_SHIFT) /* # bytes mapped by L3 ent (1G) */
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#define NBPD_L4 (1ULL << L4_SHIFT) /* # bytes mapped by L4 ent (512G) */
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#define L4_MASK 0x0000ff8000000000
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#define L3_MASK 0x0000007fc0000000
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#define L2_MASK 0x000000003fe00000
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#define L1_MASK 0x00000000001ff000
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#define L4_FRAME L4_MASK
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#define L3_FRAME (L4_FRAME|L3_MASK)
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#define L2_FRAME (L3_FRAME|L2_MASK)
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#define L1_FRAME (L2_FRAME|L1_MASK)
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/*
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* PDE/PTE bits. These are no different from their i386 counterparts.
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*/
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#define PG_V 0x0000000000000001 /* valid */
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#define PG_RO 0x0000000000000000 /* read-only */
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#define PG_RW 0x0000000000000002 /* read-write */
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#define PG_u 0x0000000000000004 /* user accessible */
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#define PG_PROT 0x0000000000000006
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#define PG_N 0x0000000000000018 /* non-cacheable */
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#define PG_U 0x0000000000000020 /* used */
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#define PG_M 0x0000000000000040 /* modified */
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#define PG_PS 0x0000000000000080 /* 2MB page size */
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#define PG_G 0x0000000000000100 /* not flushed */
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#define PG_AVAIL1 0x0000000000000200
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#define PG_AVAIL2 0x0000000000000400
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#define PG_AVAIL3 0x0000000000000800
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#define PG_FRAME 0xfffffffffffff000
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#define PG_LGFRAME 0xffffffffffc00000 /* large (2M) page frame mask */
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/*
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* short forms of protection codes
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*/
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#define PG_KR 0x0000000000000000 /* kernel read-only */
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#define PG_KW 0x0000000000000002 /* kernel read-write */
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/*
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* page protection exception bits
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*/
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#define PGEX_P 0x01 /* protection violation (vs. no mapping) */
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#define PGEX_W 0x02 /* exception during a write cycle */
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#define PGEX_U 0x04 /* exception while in user mode (upl) */
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#endif /* _X86_64_PTE_H_ */
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