147 lines
5.7 KiB
C
147 lines
5.7 KiB
C
/* $NetBSD: mb86950reg.h,v 1.3 2005/12/11 12:21:27 christos Exp $ */
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/*
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* Copyright (c) 1995 Mika Kortelainen
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mika Kortelainen
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Adapted from if_qnreg.h for the amiga port of NetBSD by Dave J. Barnes, 2004.
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*/
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/*
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* The Fujitsu mb86950, "EtherStar", is the predecessor to the mb8696x
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* NICE supported by the ate driver. While similar in function and
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* programming to the mb8696x, the register offset differences and
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* quirks make it nearly impossible to have one driver for both the
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* EtherStar and NICE chips.
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*
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* Definitions from Fujitsu documentation.
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*/
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#define ESTAR_DLCR0 0 /* Transmit status */
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#define DLCR_TX_STAT ESTAR_DLCR0
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#define ESTAR_DLCR1 1 /* Transmit masks */
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#define DLCR_TX_INT_EN ESTAR_DLCR1
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/* DLCR0/1 - Transmit Status & Masks */
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#define TX_DONE 0x80 /* Transmit okay */
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/* bit 6 - Net Busy, carrier sense ? */
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/* bit 5 - Transmit packet received ? */
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#define TX_CR_LOST 0x10 /* Carrier lost while attempting to transmit */
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#define TX_UNDERFLO 0x08 /* fifo underflow */
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#define TX_COL 0x04 /* Collision */
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#define TX_16COL 0x02 /* 16 collision */
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#define TX_BUS_WR_ERR 0x01 /* Bus write error, fifo overflo */
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#define CLEAR_TX_ERR (TX_UNDERFLO | TX_COL | TX_16COL | TX_BUS_WR_ERR) /* Clear transmit errors */
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#define TX_MASK (TX_DONE | TX_16COL)
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#define ESTAR_DLCR2 2 /* Receive status */
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#define DLCR_RX_STAT ESTAR_DLCR2
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#define ESTAR_DLCR3 3 /* Receive masks */
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#define DLCR_RX_INT_EN ESTAR_DLCR3
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/* DLCR2/3 - Receive Status & Masks */
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#define RX_PKT 0x80 /* Packet ready */
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#define RX_BUS_RD_ERR 0x40 /* fifo underflow, harmless, normally masked off */
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/* bit 5 - DMA end of process ? */
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/* bit 4 - remote control packet rx ? */
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#define RX_SHORT_ERR 0x08 /* Short packet */
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#define RX_ALIGN_ERR 0x04 /* Alignment error */
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#define RX_CRC_ERR 0x02 /* CRC error */
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#define RX_OVERFLO 0x01 /* Receive buf overflow */
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#define CLEAR_RX_ERR RX_MASK /* Clear receive and errors */
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#define RX_MASK (RX_PKT | RX_SHORT_ERR | RX_ALIGN_ERR | RX_CRC_ERR | RX_OVERFLO | RX_BUS_RD_ERR)
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#define RX_ERR_MASK (RX_SHORT_ERR | RX_ALIGN_ERR | RX_CRC_ERR | RX_OVERFLO | RX_BUS_RD_ERR)
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#define ESTAR_DLCR4 4 /* Transmit mode */
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#define DLCR_TX_MODE ESTAR_DLCR4
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/* DLCR4 - Transmit Mode */
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/* bits 7, 6, 5, 4 - collision count ? */
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#define COL_MASK 0xf0
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/* bit 3 - nc */
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/* bit 2 - gen output ? */
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#define LBC 0x02 /* Loopback control */
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/* bit 0 - defer ?, normally 0 */
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#define ESTAR_DLCR5 5 /* Receive mode */
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#define DLCR_RX_MODE ESTAR_DLCR5
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/* DLCR5 - Receive Mode */
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/* Normal mode: accept physical address, broadcast address.
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*/
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/* bit 7 - Disable CRC test mode */
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#define RX_BUF_EMTY 0x40 /* Buffer empty */
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/* bit 5 - accept packet with errors or nc ?, normally set to 0 */
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/* bit 4 - 40 bit address ?, normally set to 0 */
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/* bit 3 - accept runts ?, normally set to 0 */
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/* bit 2 - remote reset ? normally set to 0 */
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/* bit 1 & 0 - address filter mode */
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/* 00 = reject */
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/* 01 = normal mode */
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#define NORMAL_MODE 0x01
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/* 10 = ? */
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/* 11 = promiscuous mode */
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#define PROMISCUOUS_MODE 0x03 /* Accept all packets */
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#define ESTAR_DLCR6 6 /* Software reset */
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#define DLCR_CONFIG ESTAR_DLCR6
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/* DLCR6 - Enable Data Link Controller */
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#define DISABLE_DLC 0x80 /* Disable data link controller */
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#define ENABLE_DLC 0x00 /* Enable data link controller */
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#define ESTAR_DLCR7 7 /* TDR (LSB) */
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#define ESTAR_DLCR8 8 /* Node ID0 */
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#define DLCR_NODE_ID ESTAR_DLCR8
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#define ESTAR_DLCR9 9 /* Node ID1 */
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#define ESTAR_DLCR10 10 /* Node ID2 */
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#define ESTAR_DLCR11 11 /* Node ID3 */
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#define ESTAR_DLCR12 12 /* Node ID4 */
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#define ESTAR_DLCR13 13 /* Node ID5 */
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#define ESTAR_DLCR15 15 /* TDR (MSB) */
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/* The next three are usually accessed as words */
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#define ESTAR_BMPR0 16 /* Buffer memory port (FIFO) */
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#define BMPR_FIFO ESTAR_BMPR0
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#define ESTAR_BMPR2 18 /* Packet length */
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#define BMPR_TX_LENGTH ESTAR_BMPR2
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/* BMPR2:BMPR3 - Packet Length Registers (Write-only) */
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#define TRANSMIT_START 0x8000
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#define ESTAR_BMPR4 20 /* DMA enable */
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#define BMPR_DMA ESTAR_BMPR4
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