556 lines
18 KiB
C
556 lines
18 KiB
C
/* $NetBSD: elink3reg.h,v 1.31 2006/11/05 05:57:53 itohy Exp $ */
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/*
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* Copyright (c) 1995 Herb Peyerl <hpeyerl@beer.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Herb Peyerl.
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* 4. The name of Herb Peyerl may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* These define the EEPROM data structure. They are used in the probe
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* function to verify the existence of the adapter after having sent
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* the ID_Sequence.
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*/
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#define EEPROM_NODE_ADDR_0 0x0 /* Word */
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#define EEPROM_NODE_ADDR_1 0x1 /* Word */
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#define EEPROM_NODE_ADDR_2 0x2 /* Word */
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#define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
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#define EEPROM_MFG_DATE 0x4 /* Manufacturing date */
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#define EEPROM_MFG_DIVSION 0x5 /* Manufacturing division */
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#define EEPROM_MFG_PRODUCT 0x6 /* Product code */
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#define EEPROM_MFG_ID 0x7 /* 0x6d50 */
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#define EEPROM_ADDR_CFG 0x8 /* Base addr */
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#define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
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#define EEPROM_OEM_ADDR0 0xa
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#define EEPROM_OEM_ADDR1 0xb
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#define EEPROM_OEM_ADDR2 0xc
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#define EEPROM_SOFTINFO 0xd
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#define EEPROM_COMPAT 0xe
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#define EEPROM_SOFTINFO2 0xf
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#define EEPROM_CAP 0x10
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#define EEPROM_CONFIG_LOW 0x12
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#define EEPROM_CONFIG_HIGH 0x13
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#define EEPROM_SSI 0x14
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#define EEPROM_CHECKSUM_EL3 0x17
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/*
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* These are the registers for the 3Com 3c509 and their bit patterns when
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* applicable. They have been taken out of the "EtherLink III Parallel
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* Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual
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* from 3com.
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*/
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#define ELINK_COMMAND 0x0e /* Write. BASE+0x0e is always a command reg. */
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#define ELINK_STATUS 0x0e /* Read. BASE+0x0e is always status reg. */
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#define ELINK_WINDOW 0x0f /* Read. BASE+0x0f is always window reg. */
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/*
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* Corkscrew ISA Bridge ASIC registers.
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*/
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#define CORK_ASIC_DCR 0x2000
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#define CORK_ASIC_RCR 0x2002
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#define CORK_ASIC_ROM_PAGE 0x2004 /* 8-bit */
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#define CORK_ASIC_MCR 0x2006 /* 8-bit */
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#define CORK_ASIC_DEBUG 0x2008 /* 8-bit */
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#define CORK_ASIC_EEPROM_COMMAND 0x200a
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#define CORK_ASIC_EEPROM_DATA 0x200c
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/*
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* Corkscrew DMA Control Register.
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*/
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#define DCR_CHRDYWAIT_40ns (0 << 13)
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#define DCR_CHRDYWAIT_80ns (1 << 13)
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#define DCR_CHRDYWAIT_120ns (2 << 13)
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#define DCR_CHRDYWAIT_160ns (3 << 13)
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#define DCR_RECOVWAIT_80ns (0 << 11)
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#define DCR_RECOVWAIT_120ns (1 << 11)
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#define DCR_RECOVWAIT_160ns (2 << 11)
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#define DCR_RECOVWAIT_200ns (3 << 11)
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#define DCR_CMDWIDTH(x) ((x) << 8) /* base 40ns, 40ns increments */
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#define DCR_BURSTLEN(x) ((x) << 3)
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#define DCR_DRQSELECT(x) ((x) << 0) /* 3, 5, 6, 7 valid */
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/*
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* Corkscrew Debug register.
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*/
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#define DEBUG_PCIBUSFAULT (1U << 0)
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#define DEBUG_ISABUSFAULT (1U << 1)
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/*
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* Corkscrew EEPROM Command register.
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*/
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#define CORK_EEPROM_BUSY (1U << 9)
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#define CORK_EEPROM_CMD_READ (1U << 7) /* Same as 3c509 */
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/*
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* Corkscrew Master Control register.
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*/
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#define MCR_PCI_CONFIG (1U << 0)
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#define MCR_WRITE_BUFFER (1U << 1)
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#define MCR_READ_PREFETCH (1U << 2)
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/*
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* Window 0 registers. Setup.
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*/
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/* Write */
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#define ELINK_W0_EEPROM_DATA 0x0c
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#define ELINK_W0_EEPROM_COMMAND 0x0a
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#define ELINK_W0_RESOURCE_CFG 0x08
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#define ELINK_W0_ADDRESS_CFG 0x06
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#define ELINK_W0_CONFIG_CTRL 0x04
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/* Read */
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#define ELINK_W0_PRODUCT_ID 0x02
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#define ELINK_W0_MFG_ID 0x00
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/*
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* Window 1 registers. Operating Set.
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*/
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/* Write */
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#define ELINK_W1_TX_PIO_WR_2 0x02
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#define ELINK_W1_TX_PIO_WR_1 0x00
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/* Read */
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#define ELINK_W1_FREE_TX 0x0c
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#define ELINK_W1_TX_STATUS 0x0a
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#define ELINK_W1_RX_STATUS 0x08
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#define ELINK_W1_RX_ERRORS 0x04
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#define ELINK_W1_RX_PIO_RD_2 0x02
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#define ELINK_W1_RX_PIO_RD_1 0x00
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/*
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* Special registers used by the RoadRunner. These are used to program
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* a FIFO buffer to reduce the PCMCIA->PCI bridge latency during PIO.
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*/
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#define ELINK_W1_RUNNER_RDCTL 0x16
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#define ELINK_W1_RUNNER_WRCTL 0x1c
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/*
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* Window 2 registers. Station Address Setup/Read
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*/
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/* Read/Write */
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#define ELINK_W2_RECVMASK_0 0x06
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#define ELINK_W2_ADDR_5 0x05
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#define ELINK_W2_ADDR_4 0x04
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#define ELINK_W2_ADDR_3 0x03
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#define ELINK_W2_ADDR_2 0x02
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#define ELINK_W2_ADDR_1 0x01
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#define ELINK_W2_ADDR_0 0x00
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/*
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* Window 3 registers. Configuration and FIFO Management.
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*/
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/* Read */
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#define ELINK_W3_FREE_TX 0x0c
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#define ELINK_W3_FREE_RX 0x0a
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/* Read/Write, at least on busmastering cards. */
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#define ELINK_W3_INTERNAL_CONFIG 0x00 /* 32 bits */
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#define ELINK_W3_OTHER_INT 0x04 /* 8 bits */
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#define ELINK_W3_PIO_RESERVED 0x05 /* 8 bits */
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#define ELINK_W3_MAC_CONTROL 0x06 /* 16 bits */
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#define ELINK_W3_RESET_OPTIONS 0x08 /* 16 bits */
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/*
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* Window 4 registers. Diagnostics.
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*/
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/* Read/Write */
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#define ELINK_W4_MEDIA_TYPE 0x0a
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#define ELINK_W4_CTRLR_STATUS 0x08
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#define ELINK_W4_NET_DIAG 0x06
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#define ELINK_W4_FIFO_DIAG 0x04
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#define ELINK_W4_HOST_DIAG 0x02
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#define ELINK_W4_TX_DIAG 0x00
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/*
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* Window 4 offset 8 is the PHY Management register on the
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* 3c90x.
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*/
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#define ELINK_W4_BOOM_PHYSMGMT 0x08
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#define PHYSMGMT_CLK 0x0001
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#define PHYSMGMT_DATA 0x0002
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#define PHYSMGMT_DIR 0x0004
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/*
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* Window 5 Registers. Results and Internal status.
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*/
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/* Read */
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#define ELINK_W5_READ_0_MASK 0x0c
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#define ELINK_W5_INTR_MASK 0x0a
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#define ELINK_W5_RX_FILTER 0x08
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#define ELINK_W5_RX_EARLY_THRESH 0x06
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#define ELINK_W5_TX_AVAIL_THRESH 0x02
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#define ELINK_W5_TX_START_THRESH 0x00
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/*
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* Window 6 registers. Statistics.
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*/
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/* Read/Write */
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#define TX_TOTAL_OK 0x0c
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#define RX_TOTAL_OK 0x0a
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#define UPPER_FRAMES_OK 0x09
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#define TX_DEFERRALS 0x08
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#define RX_FRAMES_OK 0x07
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#define TX_FRAMES_OK 0x06
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#define RX_OVERRUNS 0x05
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#define TX_COLLISIONS 0x04
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#define TX_AFTER_1_COLLISION 0x03
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#define TX_AFTER_X_COLLISIONS 0x02
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#define TX_NO_SQE 0x01
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#define TX_CD_LOST 0x00
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/*
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* Window 7 registers.
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* Address and length for a single bus-master DMA transfer.
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* Unused for elink3 cards.
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*/
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#define ELINK_W7_MASTER_ADDRES 0x00
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#define ELINK_W7_RX_ERROR 0x04
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#define ELINK_W7_MASTER_LEN 0x06
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#define ELINK_W7_RX_STATUS 0x08
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#define ELINK_W7_MASTER_STATUS 0x0c
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/*
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* Register definitions.
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*/
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/*
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* Command register. All windows.
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*
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* 16 bit register.
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* 15-11: 5-bit code for command to be executed.
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* 10-0: 11-bit arg if any. For commands with no args;
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* this can be set to anything.
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*/
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/* Wait at least 1ms after issuing */
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#define GLOBAL_RESET (u_int16_t) 0x0000
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#define WINDOW_SELECT (u_int16_t) (0x01<<11)
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/*
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* Read ADDR_CFG reg to determine whether this is needed. If so; wait 800
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* uSec before using transceiver.
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*/
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#define START_TRANSCEIVER (u_int16_t) (0x02<<11)
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/* state disabled on power-up */
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#define RX_DISABLE (u_int16_t) (0x03<<11)
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#define RX_ENABLE (u_int16_t) (0x04<<11)
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#define RX_RESET (u_int16_t) (0x05<<11)
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#define RX_DISCARD_TOP_PACK (u_int16_t) (0x08<<11)
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#define TX_ENABLE (u_int16_t) (0x09<<11)
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#define TX_DISABLE (u_int16_t) (0x0a<<11)
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#define TX_RESET (u_int16_t) (0x0b<<11)
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#define REQ_INTR (u_int16_t) (0x0c<<11)
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#define ACK_INTR (u_int16_t) (0x0d<<11)
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#define SET_INTR_MASK (u_int16_t) (0x0e<<11)
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/* busmastering-cards only? */
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#define STATUS_ENABLE (u_int16_t) (0x0f<<11)
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#define SET_RD_0_MASK (u_int16_t) (0x0f<<11)
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#define SET_RX_FILTER (u_int16_t) (0x10<<11)
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# define FIL_INDIVIDUAL (u_int16_t) (0x01)
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# define FIL_MULTICAST (u_int16_t) (0x02)
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# define FIL_BRDCST (u_int16_t) (0x04)
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# define FIL_PROMISC (u_int16_t) (0x08)
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#define SET_RX_EARLY_THRESH (u_int16_t) (0x11<<11)
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#define SET_TX_AVAIL_THRESH (u_int16_t) (0x12<<11)
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#define SET_TX_START_THRESH (u_int16_t) (0x13<<11)
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#define START_DMA (u_int16_t) (0x14<<11) /* busmaster-only */
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# define START_DMA_TX (START_DMA | 0x0)) /* busmaster-only */
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# define START_DMA_RX (START_DMA | 0x1) /* busmaster-only */
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#define STATS_ENABLE (u_int16_t) (0x15<<11)
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#define STATS_DISABLE (u_int16_t) (0x16<<11)
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#define STOP_TRANSCEIVER (u_int16_t) (0x17<<11)
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/* Only on adapters that support power management: */
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#define POWERUP (u_int16_t) (0x1b<<11)
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#define POWERDOWN (u_int16_t) (0x1c<<11)
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#define POWERAUTO (u_int16_t) (0x1d<<11)
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/*
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* Command parameter that disables threshold interrupts
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* PIO (3c509) cards use 2044. The fifo word-oriented and 2044--2047 work.
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* "busmastering" cards need 8188.
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* The implicit two-bit upshift done by busmastering cards means
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* a value of 2047 disables threshold interrupts on both.
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*/
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#define ELINK_THRESH_DISABLE 2047
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/*
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* Status register. All windows.
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*
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* 15-13: Window number(0-7).
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* 12: Command_in_progress.
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* 11: reserved / DMA in progress on busmaster cards.
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* 10: reserved.
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* 9: reserved.
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* 8: reserved / DMA done on busmaster cards.
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* 7: Update Statistics.
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* 6: Interrupt Requested.
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* 5: RX Early.
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* 4: RX Complete.
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* 3: TX Available.
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* 2: TX Complete.
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* 1: Adapter Failure.
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* 0: Interrupt Latch.
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*/
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#define INTR_LATCH (u_int16_t) (0x0001)
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#define CARD_FAILURE (u_int16_t) (0x0002)
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#define TX_COMPLETE (u_int16_t) (0x0004)
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#define TX_AVAIL (u_int16_t) (0x0008)
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#define RX_COMPLETE (u_int16_t) (0x0010)
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#define RX_EARLY (u_int16_t) (0x0020)
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#define INT_RQD (u_int16_t) (0x0040)
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#define UPD_STATS (u_int16_t) (0x0080)
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#define DMA_DONE (u_int16_t) (0x0100) /* DMA cards only */
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#define DMA_IN_PROGRESS (u_int16_t) (0x0800) /* DMA cards only */
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#define COMMAND_IN_PROGRESS (u_int16_t) (0x1000)
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#define ALL_INTERRUPTS (CARD_FAILURE | TX_COMPLETE | TX_AVAIL | RX_COMPLETE | \
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RX_EARLY | INT_RQD | UPD_STATS)
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#define WATCHED_INTERRUPTS (CARD_FAILURE | TX_COMPLETE | RX_COMPLETE | TX_AVAIL)
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/*
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* FIFO Registers. RX Status.
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*
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* 15: Incomplete or FIFO empty.
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* 14: 1: Error in RX Packet 0: Incomplete or no error.
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* 14-11: Type of error. [14-11]
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* 1000 = Overrun.
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* 1011 = Run Packet Error.
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* 1100 = Alignment Error.
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* 1101 = CRC Error.
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* 1001 = Oversize Packet Error (>1514 bytes)
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* 0010 = Dribble Bits.
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* (all other error codes, no errors.)
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*
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* 10-0: RX Bytes (0-1514)
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*/
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#define ERR_INCOMPLETE (u_int16_t) (0x8000)
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#define ERR_RX (u_int16_t) (0x4000)
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#define ERR_MASK (u_int16_t) (0x7800)
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#define ERR_OVERRUN (u_int16_t) (0x4000)
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#define ERR_RUNT (u_int16_t) (0x5800)
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#define ERR_ALIGNMENT (u_int16_t) (0x6000)
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#define ERR_CRC (u_int16_t) (0x6800)
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#define ERR_OVERSIZE (u_int16_t) (0x4800)
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#define ERR_DRIBBLE (u_int16_t) (0x1000)
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/*
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* TX Status
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*
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* Reports the transmit status of a completed transmission. Writing this
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* register pops the transmit completion stack.
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*
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* Window 1/Port 0x0b.
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*
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* 7: Complete
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* 6: Interrupt on successful transmission requested.
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* 5: Jabber Error (TP Only, TX Reset required. )
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* 4: Underrun (TX Reset required. )
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* 3: Maximum Collisions.
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* 2: TX Status Overflow.
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* 1-0: Undefined.
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*
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*/
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#define TXS_COMPLETE 0x8000
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#define TXS_INTR_REQ 0x4000
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#define TXS_JABBER 0x2000
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#define TXS_UNDERRUN 0x1000
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#define TXS_MAX_COLLISION 0x0800
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#define TXS_STATUS_OVERFLOW 0x0400
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#define TXS_RECLAIM 0x0200
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#define TXS_TIMER 0x00ff
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/*
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* RX status
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* Window 1/Port 0x08.
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*/
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#define RX_BYTES_MASK (u_int16_t) (0x07ff)
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/*
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* Internal Config and MAC control (Window 3)
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* Window 3 / Port 0: 32-bit internal config register:
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* bits 0-2: fifo buffer ram size
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* 3: ram width (word/byte) (ro)
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* 4-5: ram speed
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* 6-7: rom size
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* 8-15: reserved
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*
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* 16-17: ram split (5:3, 3:1, or 1:1).
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* 18-19: reserved
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* 20-22: selected media type
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* 21: unused
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* 24: (nonvolatile) driver should autoselect media
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* 25-31: reserved
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*
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* The low-order 16 bits should generally not be changed by software.
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* Offsets defined for two 16-bit words, to help out 16-bit busses.
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*/
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#define CONFIG_RAMSIZE (u_int16_t) 0x0007
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#define CONFIG_RAMSIZE_SHIFT 0
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#define CONFIG_RAMWIDTH (u_int16_t) 0x0008
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#define CONFIG_RAMWIDTH_SHIFT 3
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#define CONFIG_RAMSPEED (u_int16_t) 0x0030
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#define CONFIG_RAMSPEED_SHIFT 4
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#define CONFIG_ROMSIZE (u_int16_t) 0x00c0
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#define CONFIG_ROMSIZE_SHIFT 6
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/* Window 3/port 2 */
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#define CONFIG_RAMSPLIT (u_int16_t) 0x0003
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#define CONFIG_RAMSPLIT_SHIFT 0
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#define CONFIG_MEDIAMASK (u_int16_t) 0x0070
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#define CONFIG_MEDIAMASK_SHIFT 4
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#define CONFIG_AUTOSELECT (u_int16_t) 0x0100
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#define CONFIG_AUTOSELECT_SHIFT 8
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/*
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* MAC_CONTROL (Window 3)
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*/
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#define MAC_CONTROL_FDX 0x20 /* full-duplex mode */
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/* Active media in INTERNAL_CONFIG media bits */
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#define ELINKMEDIA_10BASE_T (u_int16_t) 0x00
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#define ELINKMEDIA_AUI (u_int16_t) 0x01
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#define ELINKMEDIA_RESV1 (u_int16_t) 0x02
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#define ELINKMEDIA_10BASE_2 (u_int16_t) 0x03
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#define ELINKMEDIA_100BASE_TX (u_int16_t) 0x04
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#define ELINKMEDIA_100BASE_FX (u_int16_t) 0x05
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#define ELINKMEDIA_MII (u_int16_t) 0x06
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#define ELINKMEDIA_100BASE_T4 (u_int16_t) 0x07
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/*
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* RESET_OPTIONS (Window 3, on Demon/Vortex/Boomerang only)
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* also mapped to PCI configuration space on PCI adaptors.
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*
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* (same register as Vortex ELINK_W3_RESET_OPTIONS, mapped to pci-config space)
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*/
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#define ELINK_PCI_100BASE_T4 (1<<0)
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#define ELINK_PCI_100BASE_TX (1<<1)
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#define ELINK_PCI_100BASE_FX (1<<2)
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#define ELINK_PCI_10BASE_T (1<<3)
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#define ELINK_PCI_BNC (1<<4)
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#define ELINK_PCI_AUI (1<<5)
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#define ELINK_PCI_100BASE_MII (1<<6)
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#define ELINK_PCI_INTERNAL_VCO (1<<8)
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#define ELINK_PCI_MEDIAMASK (ELINK_PCI_100BASE_T4|ELINK_PCI_100BASE_TX| \
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ELINK_PCI_100BASE_FX|ELINK_PCI_10BASE_T| \
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ELINK_PCI_BNC|ELINK_PCI_AUI| \
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ELINK_PCI_100BASE_MII)
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#define ELINK_RUNNER_MII_RESET 0x4000
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#define ELINK_RUNNER_ENABLE_MII 0x8000
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/*
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* FIFO Status (Window 4)
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*
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* Supports FIFO diagnostics
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*
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* Window 4/Port 0x04.1
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*
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* 15: 1=RX receiving (RO). Set when a packet is being received
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* into the RX FIFO.
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* 14: Reserved
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* 13: 1=RX underrun (RO). Generates Adapter Failure interrupt.
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* Requires RX Reset or Global Reset command to recover.
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* It is generated when you read past the end of a packet -
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* reading past what has been received so far will give bad
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* data.
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* 12: 1=RX status overrun (RO). Set when there are already 8
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* packets in the RX FIFO. While this bit is set, no additional
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* packets are received. Requires no action on the part of
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* the host. The condition is cleared once a packet has been
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* read out of the RX FIFO.
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* 11: 1=RX overrun (RO). Set when the RX FIFO is full (there
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* may not be an overrun packet yet). While this bit is set,
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* no additional packets will be received (some additional
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* bytes can still be pending between the wire and the RX
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* FIFO). Requires no action on the part of the host. The
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* condition is cleared once a few bytes have been read out
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* from the RX FIFO.
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* 10: 1=TX overrun (RO). Generates adapter failure interrupt.
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* Requires TX Reset or Global Reset command to recover.
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* Disables Transmitter.
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* 9-8: Unassigned.
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* 7-0: Built in self test bits for the RX and TX FIFO's.
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*/
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#define FIFOS_RX_RECEIVING (u_int16_t) 0x8000
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#define FIFOS_RX_UNDERRUN (u_int16_t) 0x2000
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#define FIFOS_RX_STATUS_OVERRUN (u_int16_t) 0x1000
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#define FIFOS_RX_OVERRUN (u_int16_t) 0x0800
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#define FIFOS_TX_OVERRUN (u_int16_t) 0x0400
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/*
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* ISA/eisa CONFIG_CNTRL media-present bits.
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*/
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#define ELINK_W0_CC_AUI (1<<13)
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#define ELINK_W0_CC_BNC (1<<12)
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#define ELINK_W0_CC_UTP (1<<9)
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#define ELINK_W0_CC_MEDIAMASK (ELINK_W0_CC_AUI|ELINK_W0_CC_BNC| \
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ELINK_W0_CC_UTP)
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/* EEPROM state flags/commands */
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#define EEPROM_BUSY (1<<15)
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#define EEPROM_TST_MODE (1<<14)
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#define READ_EEPROM (1<<7)
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/* For the RoadRunner chips... */
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#define WRITE_EEPROM_RR 0x100
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#define READ_EEPROM_RR 0x200
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#define ERASE_EEPROM_RR 0x300
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/* window 4, MEDIA_STATUS bits */
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#define SQE_ENABLE 0x08 /* Enables SQE on AUI ports */
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#define JABBER_GUARD_ENABLE 0x40
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#define LINKBEAT_ENABLE 0x80
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#define DISABLE_UTP 0x0
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#define LINKBEAT_DETECT 0x800
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/*
|
|
* Misc defines for various things.
|
|
*/
|
|
#define TAG_ADAPTER 0xd0
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|
#define ACTIVATE_ADAPTER_TO_CONFIG 0xff
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|
#define ENABLE_DRQ_IRQ 0x0001
|
|
#define MFG_ID 0x506d /* `TCM' */
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|
#define PROD_ID_3C509 0x5090 /* 509[0-f] */
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#define GO_WINDOW(x) bus_space_write_2(sc->sc_iot, \
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sc->sc_ioh, ELINK_COMMAND, WINDOW_SELECT|x)
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/* Used to probe for large-packet support. */
|
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#define ELINK_LARGEWIN_PROBE ELINK_THRESH_DISABLE
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|
#define ELINK_LARGEWIN_MASK 0xffc
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