381 lines
12 KiB
C
381 lines
12 KiB
C
/* $NetBSD: qdreg.h,v 1.1 1998/03/21 10:02:39 ragge Exp $ */
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/*-
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* Copyright (c) 1982, 1986 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)qdreg.h 7.1 (Berkeley) 5/9/91
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*/
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/************************************************************************
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* *
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* Copyright (c) 1985, 1986 by *
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* Digital Equipment Corporation, Maynard, MA *
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* All rights reserved. *
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* *
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* This software is furnished under a license and may be used and *
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* copied only in accordance with the terms of such license and *
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* with the inclusion of the above copyright notice. This *
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* software or any other copies thereof may not be provided or *
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* otherwise made available to any other person. No title to and *
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* ownership of the software is hereby transferred. *
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* *
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* The information in this software is subject to change without *
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* notice and should not be construed as a commitment by Digital *
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* Equipment Corporation. *
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* *
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* Digital assumes no responsibility for the use or reliability *
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* of its software on equipment which is not supplied by Digital. *
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* *
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************************************************************************/
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/* Dragon ADDER reg map */
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/* ADDER register bit definitions */
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/* Y_SCROLL_CONSTANT */
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#define SCROLL_ERASE 0x2000
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#define ADDER_SCROLL_DOWN 0x1000
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/* ADDER status and interrupt enable registers [1], [2], [3] */
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#define DISABLE 0x0000
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#define PAUSE_COMPLETE 0x0001
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#define FRAME_SYNC 0x0002
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#define INIT_COMPLETE 0x0004
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#define RASTEROP_COMPLETE 0x0008
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#define ADDRESS_COMPLETE 0x0010
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#define RX_READY 0x0020
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#define TX_READY 0x0040
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#define ID_SCROLL_READY 0x0080
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#define TOP_CLIP 0x0100
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#define BOTTOM_CLIP 0x0200
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#define LEFT_CLIP 0x0400
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#define RIGHT_CLIP 0x0800
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#define NO_CLIP 0x1000
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#define VSYNC 0x2000
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/* ADDER command register [8], [10] */
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#define OCR_zero 0x0000
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#define Z_BLOCK0 0x0000
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#define OCRA 0x0000
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#define OCRB 0x0004
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#define RASTEROP 0x02c0
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#define PBT 0x03c0
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#define BTPZ 0x0bb0
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#define PTBZ 0x07a0
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#define DTE 0x0400
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#define S1E 0x0800
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#define S2E 0x1000
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#define VIPER_Z_LOAD 0x01A0
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#define ID_LOAD 0x0100
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#define CANCEL 0x0000
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#define LF_R1 0x0000
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#define LF_R2 0x0010
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#define LF_R3 0x0020
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#define LF_R4 0x0030
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/* ADDER rasterop mode register [9] */
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#define NORMAL 0x0000
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#define LINEAR_PATTERN 0x0002
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#define X_FILL 0x0003
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#define Y_FILL 0x0007
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#define BASELINE 0x0008
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#define HOLE_ENABLE 0x0010
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#define SRC_1_INDEX_ENABLE 0x0020
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#define DST_INDEX_ENABLE 0x0040
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#define DST_WRITE_ENABLE 0x0080
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/* ADDER source 2 size register */
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#define NO_TILE 0x0080
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/* External registers base addresses */
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#define CS_UPDATE_MASK 0x0060
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#define CS_SCROLL_MASK 0x0040
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/* VIPER registers */
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#define RESOLUTION_MODE 0x0080
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#define MEMORY_BUS_WIDTH 0x0081
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#define PLANE_ADDRESS 0x0083
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#define LU_FUNCTION_R1 0x0084
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#define LU_FUNCTION_R2 0x0085
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#define LU_FUNCTION_R3 0x0086
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#define LU_FUNCTION_R4 0x0087
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#define MASK_1 0x0088
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#define MASK_2 0x0089
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#define SOURCE 0x008a
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#define SOURCE_Z 0x0000
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#define BACKGROUND_COLOR 0x008e
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#define BACKGROUND_COLOR_Z 0x000C
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#define FOREGROUND_COLOR 0x008f
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#define FOREGROUND_COLOR_Z 0x0004
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#define SRC1_OCR_A 0x0090
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#define SRC2_OCR_A 0x0091
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#define DST_OCR_A 0x0092
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#define SRC1_OCR_B 0x0094
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#define SRC2_OCR_B 0x0095
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#define DST_OCR_B 0x0096
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/* VIPER scroll registers */
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#define SCROLL_CONSTANT 0x0082
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#define SCROLL_FILL 0x008b
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#define SCROLL_FILL_Z 0x0008
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#define LEFT_SCROLL_MASK 0x008c
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#define RIGHT_SCROLL_MASK 0x008d
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/* VIPER register bit definitions */
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#define EXT_NONE 0x0000
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#define EXT_SOURCE 0x0001
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#define EXT_M1_M2 0x0002
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#define INT_NONE 0x0000
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#define INT_SOURCE 0x0004
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#define INT_M1_M2 0x0008
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#define ID 0x0010
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#define NO_ID 0x0000
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#define WAIT 0x0020
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#define NO_WAIT 0x0000
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#define BAR_SHIFT_DELAY WAIT
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#define NO_BAR_SHIFT_DELAY NO_WAIT
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/* VIPER logical function unit codes */
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#define LF_ZEROS 0x0000
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#define LF_D_XOR_S 0x0006
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#define LF_SOURCE 0x000A
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#define LF_D_OR_S 0x000E
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#define LF_ONES 0x000F
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#define INV_M1_M2 0x0030
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#define FULL_SRC_RESOLUTION 0X00C0 /* makes second pass like first pass */
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/* VIPER scroll register [2] */
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#define SCROLL_DISABLE 0x0040
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#define SCROLL_ENABLE 0x0020
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#define VIPER_LEFT 0x0000
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#define VIPER_RIGHT 0x0010
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#define VIPER_UP 0x0040
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#define VIPER_DOWN 0x0000
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/* Adder scroll register */
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#define ADDER_UP 0x0000
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#define ADDER_DOWN 0x1000
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/* Misc scroll definitions */
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#define UP 0
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#define DOWN 1
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#define LEFT 2
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#define RIGHT 3
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#define NODIR 4
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#define SCROLL_VMAX 31
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#define SCROLL_HMAX 15
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#define NEW 2
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#define OLD 1
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#define BUSY 1
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#define DRAG 1
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#define SCROLL 0
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/* miscellaneous defines */
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#define ALL_PLANES 0xffffffff
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#define UNITY 0x1fff /* Adder scale factor */
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#define MAX_SCREEN_X 1024
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#define MAX_SCREEN_Y 864
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#define FONT_HEIGHT 32
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struct adder {
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/* adder control registers */
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u_short register_address; /* ADDER reg pntr for use by DGA */
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u_short request_enable; /* DMA request enables */
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u_short interrupt_enable; /* interrupt enables */
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u_short status; /* ADDER status bits */
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u_short reserved1; /* test function only */
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u_short spare1; /* spare address (what else?) */
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u_short reserved2; /* test function only */
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u_short id_data; /* data path to I/D bus */
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u_short command; /* ADDER chip command register */
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u_short rasterop_mode; /* sets rasterop execution modes */
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u_short cmd; /* duplicate path to above cmd reg */
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u_short reserved3; /* test function only */
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/* scroll registers */
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u_short ID_scroll_data; /* I/D bus scroll data */
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u_short ID_scroll_command; /* I/D bus scroll command */
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u_short scroll_x_min; /* X scroll min - left boundary */
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u_short scroll_x_max; /* X scroll max - right boundary */
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u_short scroll_y_min; /* Y scroll min - upper boundary */
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u_short scroll_y_max; /* Y scroll max - lower boundary */
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u_short pause; /* Y coord to set stat when scanned */
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u_short y_offset_pending; /* vertical scroll control */
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u_short y_scroll_constant;
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/* update control registers */
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u_short x_index_pending; /* x pending index */
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u_short y_index_pending; /* y pending index */
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u_short x_index_new; /* new x index */
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u_short y_index_new; /* new y index */
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u_short x_index_old; /* old x index */
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u_short y_index_old; /* old y index */
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u_short x_clip_min; /* left clipping boundary */
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u_short x_clip_max; /* right clipping boundary */
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u_short y_clip_min; /* upper clipping boundary */
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u_short y_clip_max; /* lower clipping boundary */
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u_short spare2; /* spare address (another!) */
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/* rasterop control registers */
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u_short source_1_dx; /* source #1 x vector */
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u_short source_1_dy; /* source #1 y vector*/
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u_short source_1_x; /* source #1 x origin */
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u_short source_1_y; /* source #1 y origin */
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u_short destination_x; /* destination x origin */
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u_short destination_y; /* destination y origin */
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u_short fast_dest_dx; /* destination x fast vector */
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u_short fast_dest_dy; /* destination y fast vector */
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u_short slow_dest_dx; /* destination x slow vector */
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u_short slow_dest_dy; /* destination y slow vector */
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u_short fast_scale; /* scale factor for fast vector */
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u_short slow_scale; /* scale factor for slow vector */
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u_short source_2_x; /* source #2 x origin */
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u_short source_2_y; /* source #2 y origin */
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u_short source_2_size; /* source #2 height & width */
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u_short error_1; /* error regs (?) */
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u_short error_2;
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/* screen format control registers */
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u_short y_scan_count_0; /* y scan counts for vert timing */
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u_short y_scan_count_1;
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u_short y_scan_count_2;
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u_short y_scan_count_3;
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u_short x_scan_conf; /* x scan configuration */
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u_short x_limit;
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u_short y_limit;
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u_short x_scan_count_0; /* x scan count for horiz timing */
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u_short x_scan_count_1;
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u_short x_scan_count_2;
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u_short x_scan_count_3;
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u_short x_scan_count_4;
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u_short x_scan_count_5;
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u_short x_scan_count_6;
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u_short sync_phase_adj; /* sync phase (horiz sync count) */
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};
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/*---------------------
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* DUART definitions */
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/* command definitions */
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#define EN_RCV 0x01
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#define DIS_RCV 0x02
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#define EN_XMT 0x04
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#define DIS_XMT 0x08
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#define RESET_M 0x10
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#define RESET_RCV 0x20
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#define RESET_XMT 0x30
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#define RESET_ERR 0x40
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#define RESET_BD 0x50
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#define START_BREAK 0x60
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#define STOP_BREAK 0x70
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/* interupt bit definitions */
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#define EI_XMT_A 0x01
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#define EI_RCV_A 0x02
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#define EI_XMT_B 0x10
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#define EI_RCV_B 0x20
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#define XMT_RDY_A 0x01
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#define RCV_RDY_A 0x02
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#define XMT_RDY_B 0x10
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#define RCV_RDY_B 0x20
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/* status register bit defintions */
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#define RCV_RDY 0x01
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#define FIFO_FULL 0x02
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#define XMT_RDY 0x04
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#define XMT_EMT 0x08
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#define OVER_ERR 0x10
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#define ERR_PARITY 0x20
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#define FRAME_ERR 0x40
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#define RCVD_BREAK 0x80
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struct duart {
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/* channel A - LK201 */
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short modeA; /* ch.A mode reg (read/write) */
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short statusA; /* ch.A status reg (read) */
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#define clkselA statusA /* ch.A clock slect reg (write) */
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short cmdA; /* ch.A command reg (write) */
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short dataA; /* rcv/xmt data ch.A (read/write) */
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short inchng; /* input change state reg (read) */
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#define auxctl inchng /* auxiliary control reg (write) */
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short istatus; /* interrupt status reg (read) */
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#define imask istatus /* interrupt mask reg (write) */
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short CThi; /* counter/timer hi byte (read) */
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#define CTRhi CThi /* counter/timer hi reg (write) */
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short CTlo; /* counter/timer lo byte (read) */
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#define CTRlo CTlo /* counter/timer lo reg (write) */
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/* channel B - pointing device */
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short modeB; /* ch.B mode reg (read/write) */
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short statusB; /* ch.B status reg (read) */
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#define clkselB statusB /* ch.B clock select reg (write) */
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short cmdB; /* ch.B command reg (write) */
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short dataB; /* ch.B rcv/xmt data (read/write) */
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short rsrvd;
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short inport; /* input port (read) */
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#define outconf inport /* output port config reg (write) */
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short strctr; /* start counter command (read) */
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#define setbits setctr /* output bits set command (write) */
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short stpctr; /* stop counter command (read) */
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#define resetbits stpctr /* output bits reset cmd (write) */
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};
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