154 lines
6.0 KiB
C
154 lines
6.0 KiB
C
/* $NetBSD: iocreg.h,v 1.1 2000/05/09 21:56:01 bjh21 Exp $ */
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/*
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* Copyright (c) 1997 Ben Harris.
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* Copyright (c) 1994 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* iocreg.h - Acorn IOC (Albion/VC2311) registers
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*
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* Based on arch/arm32/include/iomd.h 1.7:
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* Created : 18/09/94
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* Based on kate/display/iomd.h
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*/
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#ifndef _ARM26_IOCREG_H
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#define _ARM26_IOCREG_H
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/*
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* These addresses are intended to be inputs to bus_space functions,
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* and as such bits 0-4 here map to A[2:6] on the IOC.
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*/
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/* Read Write */
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#define IOC_CTL 0x00 /* Control Control */
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#define IOC_KBDDAT 0x01 /* Kbd receive Kbd send */
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#define IOC_IRQSTA 0x04 /* IRQ status A - */
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#define IOC_IRQRQA 0x05 /* IRQ request A IRQ clear */
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#define IOC_IRQMSKA 0x06 /* IRQ mask A IRQ mask A */
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#define IOC_IRQSTB 0x08 /* IRQ status B - */
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#define IOC_IRQRQB 0x09 /* IRQ request B - */
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#define IOC_IRQMSKB 0x0a /* IRQ mask B IRQ mask B */
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#define IOC_FIQST 0x0c /* FIQ status - */
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#define IOC_FIQRQ 0x0d /* FIQ request - */
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#define IOC_FIQMSK 0x0e /* FIQ mask FIQ mask */
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#define IOC_T0LOW 0x10 /* T0 count low T0 latch low */
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#define IOC_T0HIGH 0x11 /* T0 count high T0 latch high */
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#define IOC_T0GO 0x12 /* - T0 go command */
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#define IOC_T0LATCH 0x13 /* - T0 latch command */
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#define IOC_T1LOW 0x14 /* T1 count low T1 latch low */
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#define IOC_T1HIGH 0x15 /* T1 count high T1 latch high */
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#define IOC_T1GO 0x16 /* - T1 go command */
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#define IOC_T1LATCH 0x17 /* - T1 latch command */
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#define IOC_T2LOW 0x18 /* T2 count low T2 latch low */
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#define IOC_T2HIGH 0x19 /* T2 count high T2 latch high */
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#define IOC_T2GO 0x1a /* - T2 go command */
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#define IOC_T2LATCH 0x1b /* - T2 latch command */
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#define IOC_T3LOW 0x1c /* T3 count low T3 latch low */
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#define IOC_T3HIGH 0x1d /* T3 count high T3 latch high */
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#define IOC_T3GO 0x1e /* - T3 go command */
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#define IOC_T3LATCH 0x1f /* - T3 latch command */
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#define IOC_SIZE 0x20 /* Total amount of bus space used by the IOC */
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/* Control register bits (should most of these be defined here?) */
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#define IOC_CTL_SDA 0x01 /* IIC serial data */
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#define IOC_CTL_SCL 0x02 /* IIC serial clock */
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#define IOC_CTL_FDREADY 0x04 /* Floppy disc ready */
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#define IOC_CTL_SMUTE 0x20 /* Speaker mute */
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#define IOC_CTL_LPTACK 0x40 /* Printer acknowledge */
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#define IOC_CTL_FLYBACK 0x80 /* Video flyback */
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/* Internal control register bits */
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/* These give the current state of the edge-sensitive IRQ lines */
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#define IOC_CTL_NIF 0x04 /* Set if IF* is high (IRQ 2) */
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#define IOC_CTL_IR 0x08 /* Set if IR is high (IRQ 3) */
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/* IOC definitions of interrupt sources (independent of machine) */
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/* Hmm Interrupt numbers or masks? Numbers for now. */
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#define IOC_IRQ_IL6 0 /* Active low input */
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#define IOC_IRQ_IL7 1 /* Active low input */
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#define IOC_IRQ_IF 2 /* Falling edge-triggered */
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#define IOC_IRQ_IR 3 /* Rising edge-triggered */
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#define IOC_IRQ_POR 4 /* Power-on reset */
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#define IOC_IRQ_TM0 5 /* Timer 0 reloaded */
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#define IOC_IRQ_TM1 6 /* Timer 1 reloaded */
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#define IOC_IRQ_1 7 /* Always interrupt */
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#define IOC_IRQ_IL0 8 /* Active low input */
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#define IOC_IRQ_IL1 9 /* Active low input */
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#define IOC_IRQ_IL2 10 /* Active low input */
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#define IOC_IRQ_IL3 11 /* Active low input */
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#define IOC_IRQ_IL4 12 /* Active low input */
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#define IOC_IRQ_IL5 13 /* Active low input */
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#define IOC_IRQ_STX 14 /* KART transmit finished */
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#define IOC_IRQ_SRX 15 /* KART receive finished */
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#define IOC_IRQA_BIT(n) ((n) < 8 ? 1 << (n) : 0)
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#define IOC_IRQB_BIT(n) ((n) < 8 ? 0 : 1 << ((n) - 8))
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#define IOC_IRQ_CLEARABLE_MASK 0x7c
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/* FIQ sources */
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#define IOC_FIQ_FH0 0 /* Active high input */
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#define IOC_FIQ_FH1 1 /* Active high input */
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#define IOC_FIQ_FL 2 /* Active low input */
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#define IOC_FIQ_C3 3 /* Active low input (also ctl reg) */
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#define IOC_FIQ_C4 4 /* Active low input (also ctl reg) */
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#define IOC_FIQ_C5 5 /* Active low input (also ctl reg) */
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#define IOC_FIQ_IL0 6 /* Active low input (also IRQ) */
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#define IOC_FIQ_1 7 /* Always interrupt */
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#define IOC_FIQ_BIT(n) (1 << (n))
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/* Cycle types */
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#define IOC_TYPE_SLOW 0
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#define IOC_TYPE_MEDIUM 1
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#define IOC_TYPE_FAST 2
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#define IOC_TYPE_SYNC 3
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/* Counter decrement rate */
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#define IOC_TIMER_RATE 2000000 /* 2 MHz */
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/* Archimedes-specific defines */
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#define IOC_TYPE_SHIFT (19 - 2) /* A[20:19] -> T[1:0] */
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#define IOC_BANK_SHIFT (16 - 2) /* A[18:16] -> B[2:0] */
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#endif
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