166 lines
4.3 KiB
C
166 lines
4.3 KiB
C
/* $NetBSD: if_ecreg.h,v 1.2 2019/12/27 09:41:50 msaitoh Exp $ */
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/*
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* 3Com Etherlink II (3c503) register definitions.
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*
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* Copyright (C) 1993, David Greenman. This software may be used, modified,
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* copied, distributed, and sold, in both source and binary form provided that
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* the above copyright and these terms are retained. Under no circumstances is
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* the author responsible for the proper functioning of this software, nor does
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* the author assume any responsibility for damages incurred with its use.
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*/
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#ifndef _DEV_ISA_IF_ECREG_H_
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#define _DEV_ISA_IF_ECREG_H_
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#define ELINK2_NIC_OFFSET 0
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#define ELINK2_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
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/*
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* XXX - The I/O address range is fragmented in the 3c503; this is the
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* number of regs at iobase.
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*/
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#define ELINK2_NIC_PORTS 16
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#define ELINK2_ASIC_PORTS 16
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/* tx memory starts in second bank on 8bit cards */
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#define ELINK2_TX_PAGE_OFFSET_8BIT 0x20
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/* tx memory starts in first bank on 16bit cards */
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#define ELINK2_TX_PAGE_OFFSET_16BIT 0x0
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/* ...and rx memory starts in second bank */
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#define ELINK2_RX_PAGE_OFFSET_16BIT 0x20
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/*
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* Page Start Register. Must match PSTART in NIC.
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*/
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#define ELINK2_PSTR 0
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/*
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* Page Stop Register. Must match PSTOP in NIC.
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*/
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#define ELINK2_PSPR 1
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/*
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* DrQ Timer Register. Determines number of bytes to be transferred during a
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* DMA burst.
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*/
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#define ELINK2_DQTR 2
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/*
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* Base Configuration Register. Read-only register which contains the
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* board-configured I/O base address of the adapter. Bit encoded.
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*/
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#define ELINK2_BCFR 3
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/*
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* EPROM Configuration Register. Read-only register which contains the
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* board-configured memory base address. Bit encoded.
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*/
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#define ELINK2_PCFR 4
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/*
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* GA Configuration Register. Gate-Array Configuration Register.
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*
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* mbs2 mbs1 mbs0 start address
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* 0 0 0 0x0000
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* 0 0 1 0x2000
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* 0 1 0 0x4000
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* 0 1 1 0x6000
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*
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* Note that with adapters with only 8K, the setting for 0x2000 must always be
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* used.
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*/
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#define ELINK2_GACFR 5
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#define ELINK2_GACFR_MBS0 0x01
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#define ELINK2_GACFR_MBS1 0x02
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#define ELINK2_GACFR_MBS2 0x04
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#define ELINK2_GACFR_RSEL 0x08 /* enable shared memory */
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#define ELINK2_GACFR_TEST 0x10 /* for GA testing */
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#define ELINK2_GACFR_OWS 0x20 /* select 0WS access to GA */
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#define ELINK2_GACFR_TCM 0x40 /* Mask DMA interrupts */
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#define ELINK2_GACFR_NIM 0x80 /* Mask NIC interrupts */
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/*
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* Control Register. Miscellaneous control functions.
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*/
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#define ELINK2_CR 6
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#define ELINK2_CR_RST 0x01 /* Reset GA and NIC */
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#define ELINK2_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
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#define ELINK2_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
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#define ELINK2_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
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#define ELINK2_CR_SHARE 0x10 /* select interrupt sharing option */
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#define ELINK2_CR_DBSEL 0x20 /* Double buffer select */
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#define ELINK2_CR_DDIR 0x40 /* DMA direction select */
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#define ELINK2_CR_START 0x80 /* Start DMA controller */
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/*
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* Status Register. Miscellaneous status information.
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*/
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#define ELINK2_STREG 7
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#define ELINK2_STREG_REV 0x07 /* GA revision */
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#define ELINK2_STREG_DIP 0x08 /* DMA in progress */
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#define ELINK2_STREG_DTC 0x10 /* DMA terminal count */
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#define ELINK2_STREG_OFLW 0x20 /* Overflow */
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#define ELINK2_STREG_UFLW 0x40 /* Underflow */
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#define ELINK2_STREG_DPRDY 0x80 /* Data port ready */
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/*
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* Interrupt/DMA Configuration Register
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*/
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#define ELINK2_IDCFR 8
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#define ELINK2_IDCFR_DRQ 0x07 /* DMA request */
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#define ELINK2_IDCFR_UNUSED 0x08 /* not used */
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#if 0
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#define ELINK2_IDCFR_IRQ 0xF0 /* Interrupt request */
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#else
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#define ELINK2_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
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#define ELINK2_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
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#define ELINK2_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
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#define ELINK2_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
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#endif
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/*
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* DMA Address Register MSB
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*/
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#define ELINK2_DAMSB 9
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/*
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* DMA Address Register LSB
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*/
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#define ELINK2_DALSB 0x0a
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/*
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* Vector Pointer Register 2
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*/
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#define ELINK2_VPTR2 0x0b
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/*
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* Vector Pointer Register 1
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*/
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#define ELINK2_VPTR1 0x0c
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/*
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* Vector Pointer Register 0
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*/
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#define ELINK2_VPTR0 0x0d
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/*
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* Register File Access MSB
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*/
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#define ELINK2_RFMSB 0x0e
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/*
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* Register File Access LSB
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*/
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#define ELINK2_RFLSB 0x0f
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#endif /* _DEV_ISA_IF_ECREG_H_ */
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