232 lines
6.7 KiB
C
232 lines
6.7 KiB
C
/* $NetBSD: ncrsc_pcctwo.c,v 1.4 2000/03/18 22:33:03 scw Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Front-end attachment code for the ncr53c710 SCSI controller
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* on mvme1[67]7 boards.
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*
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* At the present time, this attaches to an MD driver; that will change
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* when bus_dma* support is added to mvme68k, and a bus_dma* aware MI
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* driver for the NCR chip is available.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <mvme68k/dev/siopreg.h>
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#include <mvme68k/dev/siopvar.h>
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#include <mvme68k/dev/pcctworeg.h>
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#include <mvme68k/dev/pcctwovar.h>
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int ncrsc_pcctwo_match __P((struct device *, struct cfdata *, void *));
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void ncrsc_pcctwo_attach __P((struct device *, struct device *, void *));
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struct cfattach ncrsc_pcctwo_ca = {
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sizeof(struct siop_softc), ncrsc_pcctwo_match, ncrsc_pcctwo_attach
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};
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static int ncrsc_pcctwo_intr __P((void *));
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static struct scsipi_device ncrsc_pcctwo_scsidev = {
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NULL, /* use default error handler */
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NULL, /* do not have a start functio */
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NULL, /* have no async handler */
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NULL, /* Use default done routine */
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};
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extern struct cfdriver ncrsc_cd;
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/*
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* Define 'scsi_nosync = 0x00' to enable sync SCSI mode.
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* (Required by the main SIOP driver. This was also used by
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* the 147's SBIC driver, but sync scsi is so unreliable on
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* that board that I disabled it permanently. '167 sync.
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* scsi appears to work very well, on the other hand.)
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*/
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u_long scsi_nosync = 0;
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int shift_nosync = 0;
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/* ARGSUSED */
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int
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ncrsc_pcctwo_match(parent, cf, args)
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struct device *parent;
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struct cfdata *cf;
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void *args;
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{
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struct pcctwo_attach_args *pa;
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pa = args;
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if (strcmp(pa->pa_name, ncrsc_cd.cd_name))
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return (0);
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pa->pa_ipl = cf->pcctwocf_ipl;
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return (1);
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}
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/* ARGSUSED */
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void
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ncrsc_pcctwo_attach(parent, self, args)
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struct device *parent;
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struct device *self;
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void *args;
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{
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struct pcctwo_attach_args *pa;
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struct siop_softc *sc;
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bus_space_handle_t bush;
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int clk, ctest7;
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int tmp;
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pa = (struct pcctwo_attach_args *) args;
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sc = (struct siop_softc *) self;
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/*
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* On the '177 the siop's clock is the same as the cpu clock.
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* On the other boards, the siop runs at twice the cpu clock.
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* Also, the 177 cannot do proper bus-snooping (the 68060 is
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* lame in this repspect) so don't enable it on that board.
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*/
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if (machineid == MVME_177) {
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clk = cpuspeed;
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ctest7 = 0;
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} else {
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clk = cpuspeed * 2;
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ctest7 = SIOP_CTEST7_SC0;
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}
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printf(": %dMHz ncr53C710 SCSI I/O Processor\n", clk);
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/* XXXSCW: This is a hack until siop is bus-spaced */
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bus_space_map(pa->pa_bust, pa->pa_offset, 0x40, 0, &bush);
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sc->sc_siopp = (siop_regmap_p) bush;
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sc->sc_clock_freq = clk;
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sc->sc_ctest7 = ctest7 | SIOP_CTEST7_TT1;
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sc->sc_dcntl = SIOP_DCNTL_EA;
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sc->sc_adapter.scsipi_cmd = siop_scsicmd;
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sc->sc_adapter.scsipi_minphys = siop_minphys;
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sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
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sc->sc_link.adapter_softc = sc;
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sc->sc_link.scsipi_scsi.adapter_target = 7; /* Could use NVRAM
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* setting */
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sc->sc_link.adapter = &sc->sc_adapter;
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sc->sc_link.device = &ncrsc_pcctwo_scsidev;
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sc->sc_link.openings = 2;
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sc->sc_link.scsipi_scsi.max_target = 7;
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sc->sc_link.scsipi_scsi.max_lun = 7;
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sc->sc_link.type = BUS_SCSI;
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/* Chip-specific initialisation */
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siopinitialize(sc);
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/* Hook the chip's interrupt */
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pcc2_reg_write(sys_pcctwo, PCC2REG_SCSI_ICSR, 0);
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pcctwointr_establish(PCCTWOV_SCSI, ncrsc_pcctwo_intr, pa->pa_ipl, sc);
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pcc2_reg_write(sys_pcctwo, PCC2REG_SCSI_ICSR,
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pa->pa_ipl | PCCTWO_ICR_IEN);
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/*
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* Attach all scsi units on us, watching for boot device
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* (see dk_establish).
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*/
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tmp = bootpart;
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if (PCCTWO_PADDR(pa->pa_offset) != bootaddr)
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bootpart = -1; /* Invalid flag to dk_establish */
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(void) config_found(self, &sc->sc_link, scsiprint);
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bootpart = tmp; /* Restore old value */
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}
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static int
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ncrsc_pcctwo_intr(arg)
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void *arg;
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{
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struct siop_softc *sc;
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siop_regmap_p rp;
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u_char istat;
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sc = arg;
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/*
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* Catch any errors which can happen when the SIOP is
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* local bus master...
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*/
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istat = pcc2_reg_read(sys_pcctwo, PCC2REG_SCSI_ERR_STATUS);
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if ((istat & PCCTWO_ERR_SR_MASK) != 0) {
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printf("%s: Local bus error: 0x%02x\n",
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sc->sc_dev.dv_xname, istat);
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istat |= PCCTWO_ERR_SR_SCLR;
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pcc2_reg_write(sys_pcctwo, PCC2REG_SCSI_ERR_STATUS, istat);
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}
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/* This is potentially nasty, since the IRQ is level triggered... */
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if (sc->sc_flags & SIOP_INTSOFF)
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return (0);
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rp = sc->sc_siopp;
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istat = rp->siop_istat;
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if ((istat & (SIOP_ISTAT_SIP | SIOP_ISTAT_DIP)) == 0)
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return (0);
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/* Save interrupt details for the back-end interrupt handler */
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sc->sc_sstat0 = rp->siop_sstat0;
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sc->sc_istat = istat;
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sc->sc_dstat = rp->siop_dstat;
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/* Deal with the interrupt */
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siopintr(sc);
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return (1);
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}
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