267 lines
7.3 KiB
Groff
267 lines
7.3 KiB
Groff
.\" $NetBSD: cpu.4,v 1.1 2014/02/24 07:23:40 skrll Exp $
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.\"
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.\" $OpenBSD: cpu.4tbl,v 1.19 2004/04/08 16:17:09 mickey Exp $
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.\"
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.\" Copyright (c) 2002 Michael Shalayeff
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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.\" IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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.\" INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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.\" (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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.\" SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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.\" STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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.\" IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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.\" THE POSSIBILITY OF SUCH DAMAGE.
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.\"
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.Dd April 4, 2002
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.Dt CPU 4 hppa
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.Os
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.Sh NAME
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.Nm cpu
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.Nd HP PA-RISC CPU
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.Sh SYNOPSIS
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.Cd "cpu* at mainbus0 irq 31"
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.Sh DESCRIPTION
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The following table lists the
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.Tn PA-RISC
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CPU types and their characteristics, such as TLB, maximum
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cache sizes and
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.Tn HP 9000/700
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machines they were used in (see also
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.Xr intro 4
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for the reverse list).
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.Pp
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.in +\n(dIu
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.TS
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tab (:) ;
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l l l l l l l
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l l l l l l l
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_ _ _ _ _ _ _
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l l l l l l l .
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CPU:PA:Clock:Caches:TLB:BTLB:Models
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: :(max):(max) : : :
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: : MHz : KB : : :
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7000:1.1a:66 : 256 L1I:96I:4 I:705,710,720
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: : : 256 L1D:96D:4 D:730,750
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7100:1.1b:100:1024 L1I:120:16:715/33/50/75
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: : :2048 L1D: : :725/50/75
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: : : : : :{735,755}/100
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: : : : : :742i, 745i, 747i
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7150:1.1b:125:1024 L1I:120:16:{735,755}/125
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: : :2048 L1D: : :
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7100LC:1.1c:100: 1 L1I:64:8:712/60/80/100
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: : :1024 L2I: : :715/64/80/100
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: : :1024 L2D: : :715/100XC
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: : : : : :725/64/100
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: : : : : :743i, 748i
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: : : : : :SAIC
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7200:1.1d:140: 2 L1 :120:16:C100,C110
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: : :1024 L2I: : :J200,J210
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: : :1024 L2D: : :
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7300LC:1.1e:180: 64 L1I:96:8:A180,A180C
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: : : 64 L1D: : :B132,B160,B180
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: : :8192 L2: : :C132L,C160L
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: : : : : :744, 745, 748
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: : : : : :RDI PrecisioBook
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.TE
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.in -\n(dIu
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.Sh FLOATING-POINT COPROCESSOR
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The following table summarizes available floating-point coprocessor
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models for the 32-bit
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.Tn PA-RISC
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processors.
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.Pp
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.in +\n(dIu
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.TS
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tab (:) ;
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l l
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_ _
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l l .
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FPU:Model
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Indigo:
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Sterling I MIU (TYCO):
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Sterling I MIU (ROC w/Weitek):
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FPC (w/Weitek):
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FPC (w/Bit):
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Timex-II:
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Rolex:725/50, 745i
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HARP-I:
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Tornado:J2x0,C1x0
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PA-50 (Hitachi):
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PCXL:712/60/80/100
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.TE
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.in -\n(dIu
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.Sh SUPERSCALAR EXECUTION
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The following table summarizes the superscalar execution capabilities
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of 32-bit
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.Tn PA-RISC
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processors.
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.Pp
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.in +\n(dIu
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.TS
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nokeep tab (:) ;
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l l l
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_ _ _
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l l l .
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CPU:Units:Bundles
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7100:1 integer ALU:load-store/fp
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:1 FP :int/fp
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: :branch/*
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7100LC:2 integer ALU:load-store/int
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:1 FP :load-store/fp
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: :int/fp
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: :branch/*
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7200:2 integer ALU:load-store/int
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:1 FP :load-store/fp
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: :int/int
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: :int/fp
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: :branch/*
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7300LC:2 integer ALU:load-store/int
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:1 FP :load-store/fp
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: :int/fp
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: :branch/*
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.TE
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.in -\n(dIu
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.Pp
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In conclusion, all of the above CPUs are dual-issue, or 2-way superscalar,
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with the exception that on CPUs with two integer ALUs only one of these
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units is capable of doing shift, load/store, and test operations.
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Additionally, there are several kinds of restrictions placed upon the
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superscalar execution:
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.Pp
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For the purpose of showing which instructions are allowed to proceed
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together through the pipeline, they are divided into classes:
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.Pp
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.in +\n(dIu
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.TS
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tab (:) ;
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l l
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_ _
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l l .
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Class:Description
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flop:floating point operation
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ldst:loads and stores
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flex:integer ALU
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mm:shifts, extracts and deposits
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nul:might nullify successor
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bv:BV, BE
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br:other branches
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fsys:FTEST and FP status/exception
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sys:system control instructions
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.TE
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.in -\n(dIu
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.Pp
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For CPUs with two integer ALUs (7100LC, 7200, 7300LC), the following
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table lists the instructions which are allowed to be executed
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concurrently:
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.Pp
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.in +\n(dIu
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.TS
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tab (:) ;
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l l
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_ _
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l l .
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First:Second instruction
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flop: + ldst/flex/mm/nul/bv/br
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ldst: + flop/flex/mm/nul/br
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flex: + flop/ldst/flex/mm/nul/br/fsys
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mm: + flop/ldst/flex/fsys
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nul: + flop
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sys: never bundled
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.TE
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.in -\n(dIu
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.Pp
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ldst + ldst is also possible under certain circumstances, which is then
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called "double word load/store".
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.Pp
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The following restrictions are placed upon the superscalar execution:
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.Pp
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.Bl -bullet -compact
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.It
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An instruction that modifies a register will not be bundled with another
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instruction that takes this register as operand.
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Exception: a flop can be bundled with an FP store of the flop's result register.
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.It
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An FP load to one word of a doubleword register will not be bundled with
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a flop that uses the other doubleword of this register.
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.It
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A flop will not be bundled with an FP load if both instructions have the
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same target register.
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.It
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An instruction that could set the carry/borrow bits will not be bundled
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with an instruction that uses
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carry/borrow bits.
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.It
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An instruction which is in the delay slot of a branch is never bundled
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with other instructions.
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.It
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An instruction which is at an odd word address and executed as a target
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of a taken branch is never bundled.
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.It
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An instruction which might nullify its successor is never bundled with
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this successor.
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Only if the successor is a flop instruction is this bundle allowed.
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.El
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.Sh PERFORMANCE MONITOR COPROCESSOR
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The performance monitor coprocessor is an optional,
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implementation-dependent coprocessor which provides a minimal common
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software interface to implementation-dependent performance monitor hardware.
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.Sh DEBUG SPECIAL UNIT
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The debug special function unit is an optional,
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architected SFU which provides hardware assistance for software debugging
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using breakpoints.
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The debug SFU is currently defined only for Level 0 processors.
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.Sh SEE ALSO
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.Xr asp 4 ,
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.Xr intro 4 ,
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.Xr lasi 4 ,
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.Xr mem 4 ,
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.Xr wax 4
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.Pp
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.Lk http://www.openpa.net/ "PA-RISC Information Resource"
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.Rs
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.%T PA-RISC 1.1 Architecture and Instruction Set Reference Manual
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.%A Hewlett-Packard
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.%D May 15, 1996
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.Re
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.Rs
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.%T PA7100LC ERS
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.%A Hewlett-Packard
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.%D March 30 1999
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.%N Public version 1.0
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.Re
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.Rs
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.%T Design of the PA7200 CPU
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.%A Hewlett-Packard Journal
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.%D February 1996
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.Re
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.Rs
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.%T PA7300LC ERS
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.%A Hewlett-Packard
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.%D March 18 1996
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.%N Version 1.0
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.Re
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.Sh HISTORY
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The
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.Nm
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driver was written by
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.An Michael Shalayeff Aq Mt mickey@openbsd.org
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for the HPPA port for
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.Ox 2.5 .
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It was ported to
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.Nx 1.6
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by Matthew Fredette.
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