73b3a64df4
(which are in mips/locore.S) into <mips/locore.h> from various MD files.
179 lines
5.1 KiB
C
179 lines
5.1 KiB
C
/* $NetBSD: intr.h,v 1.19 2007/06/17 06:04:28 tsutsui Exp $ */
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/*
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* Copyright (c) 1998 Jonathan Stone. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jonathan Stone for
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* the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HPCMIPS_INTR_H_
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#define _HPCMIPS_INTR_H_
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#include <sys/device.h>
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#include <sys/lock.h>
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#include <sys/queue.h>
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#define IPL_NONE 0 /* disable only this interrupt */
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#define IPL_SOFT 1 /* generic software interrupts (SI 0) */
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#define IPL_SOFTCLOCK 2 /* clock software interrupts (SI 0) */
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#define IPL_SOFTNET 3 /* network software interrupts (SI 1) */
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#define IPL_SOFTSERIAL 4 /* serial software interrupts (SI 1) */
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#define IPL_BIO 5 /* disable block I/O interrupts */
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#define IPL_NET 6 /* disable network interrupts */
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#define IPL_TTY 7 /* disable terminal interrupts */
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#define IPL_LPT IPL_TTY
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#define IPL_VM IPL_TTY
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#define IPL_SERIAL 7 /* disable serial hardware interrupts */
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#define IPL_CLOCK 8 /* disable clock interrupts */
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#define IPL_STATCLOCK IPL_CLOCK
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#define IPL_SCHED IPL_CLOCK
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#define IPL_HIGH 8 /* disable all interrupts */
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#define IPL_LOCK IPL_HIGH
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#define _IPL_N 9
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#define _IPL_SI0_FIRST IPL_SOFT
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#define _IPL_SI0_LAST IPL_SOFTCLOCK
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#define _IPL_SI1_FIRST IPL_SOFTNET
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#define _IPL_SI1_LAST IPL_SOFTSERIAL
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#define SI_SOFT 0
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#define SI_SOFTCLOCK 1
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#define SI_SOFTNET 2
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#define SI_SOFTSERIAL 3
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#define SI_NQUEUES 4
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#define SI_QUEUENAMES { \
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"misc", \
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"clock", \
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"net", \
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"serial", \
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}
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/* Interrupt sharing types. */
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#define IST_UNUSABLE -1 /* interrupt cannot be used */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#ifdef _KERNEL
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#ifndef _LOCORE
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#include <mips/cpuregs.h>
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#include <mips/locore.h>
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extern const u_int32_t *ipl_sr_bits;
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extern const u_int32_t ipl_si_to_sr[SI_NQUEUES];
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void intr_init(void);
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#define spl0() (void) _spllower(0)
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#define splx(s) (void) _splset(s)
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#define splsoft() _splraise(ipl_sr_bits[IPL_SOFT])
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typedef int ipl_t;
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typedef struct {
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ipl_t _sr;
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} ipl_cookie_t;
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static inline ipl_cookie_t
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makeiplcookie(ipl_t ipl)
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{
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return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
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}
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static inline int
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splraiseipl(ipl_cookie_t icookie)
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{
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return _splraise(icookie._sr);
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}
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#include <sys/spl.h>
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/*
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* software simulated interrupt
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*/
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#define setsoft(x) \
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do { \
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_setsoftintr(ipl_si_to_sr[(x)]); \
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} while (0)
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struct hpcmips_soft_intrhand {
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TAILQ_ENTRY(hpcmips_soft_intrhand)
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sih_q;
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struct hpcmips_soft_intr *sih_intrhead;
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void (*sih_fn)(void *);
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void *sih_arg;
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int sih_pending;
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};
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struct hpcmips_soft_intr {
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TAILQ_HEAD(, hpcmips_soft_intrhand)
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softintr_q;
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struct evcnt softintr_evcnt;
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struct simplelock softintr_slock;
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unsigned long softintr_siq;
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};
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void softintr_init(void);
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void softintr(u_int32_t);
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void *softintr_establish(int, void (*)(void *), void *);
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void softintr_disestablish(void *);
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void softintr_dispatch(void);
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#define softintr_schedule(arg) \
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do { \
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struct hpcmips_soft_intrhand *__sih = (arg); \
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struct hpcmips_soft_intr *__si = __sih->sih_intrhead; \
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int __s; \
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\
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__s = splhigh(); \
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simple_lock(&__si->softintr_slock); \
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if (__sih->sih_pending == 0) { \
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TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \
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__sih->sih_pending = 1; \
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setsoft(__si->softintr_siq); \
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} \
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simple_unlock(&__si->softintr_slock); \
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splx(__s); \
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} while (0)
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/* XXX For legacy software interrupts. */
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extern struct hpcmips_soft_intrhand *softnet_intrhand;
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#define setsoftnet() softintr_schedule(softnet_intrhand)
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#endif /* !_LOCORE */
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#endif /* _KERNEL */
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#endif /* !_HPCMIPS_INTR_H_ */
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