67 lines
2.5 KiB
C
67 lines
2.5 KiB
C
/* $NetBSD: if_lereg.h,v 1.9 1998/01/11 21:57:03 thorpej Exp $ */
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/*
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)if_lereg.h 7.1 (Berkeley) 5/8/90
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*/
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/*
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* DIO registers, offsets from lestd[0]
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*/
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#define LER0_ID 0x01 /* ID */
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#define LER0_STATUS 0x03 /* interrupt enable/status */
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#define LER0_SIZE 4
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/*
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* Control and status bits -- LER0_STATUS
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*/
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#define LE_IE 0x80 /* interrupt enable */
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#define LE_IR 0x40 /* interrupt requested */
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#define LE_LOCK 0x08 /* lock status register */
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#define LE_ACK 0x04 /* ack of lock */
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#define LE_JAB 0x02 /* loss of tx clock (???) */
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/*
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* LANCE registers, offsets from lestd[1]
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*/
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#define LER1_RDP 0x00 /* data port */
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#define LER1_RAP 0x02 /* register select port */
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#define LER1_SIZE 4
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/*
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* LANCE buffer area.
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*/
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#define LE_BUFSIZE 16384
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