278 lines
9.0 KiB
C
278 lines
9.0 KiB
C
/* $NetBSD: cpu.h,v 1.5 1998/11/24 12:49:14 mrg Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cpu.h 8.4 (Berkeley) 1/5/94
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*/
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#ifndef _CPU_H_
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#define _CPU_H_
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_MAXID 1 /* no valid machdep ids */
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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}
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#ifdef _KERNEL
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/*
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* Exported definitions unique to SPARC cpu support.
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*/
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#include <machine/psl.h>
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#include <machine/reg.h>
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#include <sparc64/sparc64/intreg.h>
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define cpu_swapin(p) /* nothing */
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#define cpu_swapout(p) /* nothing */
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#define cpu_wait(p) /* nothing */
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/*
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* Arguments to hardclock, softclock and gatherstats encapsulate the
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* previous machine state in an opaque clockframe. The ipl is here
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* as well for strayintr (see locore.s:interrupt and intr.c:strayintr).
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* Note that CLKF_INTR is valid only if CLKF_USERMODE is false.
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*/
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/*
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* Note: we have to do something to make sure this matches the definition
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* of trapframe in reg.h.
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*/
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#if 0
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struct clockframe {
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u_int64_t tstate; /* pstate before interrupt, excluding PSR_ET */
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u_int64_t pc; /* pc at interrupt */
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u_int64_t npc; /* npc at interrupt */
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u_int64_t faultaddr; /* faulting addr -- not used */
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u_int64_t oldfp; /* location of prev trapframe */
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u_int pil; /* actual interrupt priority level */
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u_int oldpil; /* priority before interrupt */
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u_int64_t fp; /* %fp at interrupt */
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};
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typedef const struct clockframe clockframe;
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extern int eintstack[];
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#define CLKF_USERMODE(framep) (((framep)->tstate & TSTATE_PRIV) == 0)
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#define CLKF_BASEPRI(framep) (((framep)->oldpil) == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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#define CLKF_INTR(framep) (((framep)->fp < (u_int)eintstack)&&((framep)->fp > (u_int)KERNBASE))
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#else
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extern int eintstack[];
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struct clockframe {
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struct trapframe t;
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};
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#define CLKF_USERMODE(framep) (((framep)->t.tf_tstate & TSTATE_PRIV) == 0)
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#define CLKF_BASEPRI(framep) (((framep)->t.tf_oldpil) == 0)
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#define CLKF_PC(framep) ((framep)->t.tf_pc)
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#define CLKF_INTR(framep) (((framep)->t.tf_kstack < (u_int)eintstack)&&((framep)->t.tf_kstack > (u_int)KERNBASE))
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#endif
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/*
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* Software interrupt request `register'.
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*/
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union sir {
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int sir_any;
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char sir_which[4];
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} sir;
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#define SIR_NET 0
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#define SIR_CLOCK 1
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#define setsoftint() ienab_bis(IE_L1)
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#define setsoftnet() (sir.sir_which[SIR_NET] = 1, setsoftint())
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#define setsoftclock() (sir.sir_which[SIR_CLOCK] = 1, setsoftint())
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int want_ast;
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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int want_resched; /* resched() was called */
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#define need_resched() (want_resched = 1, want_ast = 1)
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/*
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* Give a profiling tick to the current process when the user profiling
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* buffer pages are invalid. On the sparc, request an ast to send us
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* through trap(), marking the proc as needing a profiling tick.
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*/
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#define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1)
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define signotify(p) (want_ast = 1)
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/*
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* Only one process may own the FPU state.
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*
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* XXX this must be per-cpu (eventually)
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*/
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struct proc *fpproc; /* FPU owner */
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int foundfpu; /* true => we have an FPU */
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/*
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* Interrupt handler chains. Interrupt handlers should return 0 for
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* ``not me'' or 1 (``I took care of it''). intr_establish() inserts a
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* handler into the list. The handler is called with its (single)
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* argument, or with a pointer to a clockframe if ih_arg is NULL.
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*/
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struct intrhand {
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int (*ih_fun) __P((void *));
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void *ih_arg;
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short ih_number; /* interrupt number the H/W provides */
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short ih_pil; /* interrupt priority */
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struct intrhand *ih_next;
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u_int64_t *ih_map; /* Interrupt map register */
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u_int64_t *ih_clr; /* clear interrupt register */
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};
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extern struct intrhand *intrhand[15];
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extern struct intrhand *intrlev[MAXINTNUM];
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void intr_establish __P((int level, struct intrhand *));
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/*
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* intr_fasttrap() is a lot like intr_establish, but is used for ``fast''
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* interrupt vectors (vectors that are not shared and are handled in the
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* trap window). Such functions must be written in assembly.
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*
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* This should be removed for sun4u.
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*/
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void intr_fasttrap __P((int level, void (*vec)(void)));
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/* disksubr.c */
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struct dkbad;
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int isbad __P((struct dkbad *bt, int, int, int));
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/* machdep.c */
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int ldcontrolb __P((caddr_t));
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void dumpconf __P((void));
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caddr_t reserve_dumppages __P((caddr_t));
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/* clock.c */
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struct timeval;
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void lo_microtime __P((struct timeval *));
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int statintr __P((void *));
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int clockintr __P((void *));/* level 10 (clock) interrupt code */
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int statintr __P((void *)); /* level 14 (statclock) interrupt code */
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/* locore.s */
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struct fpstate;
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void savefpstate __P((struct fpstate *));
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void loadfpstate __P((struct fpstate *));
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int probeget __P((caddr_t, int));
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#if 0
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void write_all_windows __P((void));
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void write_user_windows __P((void));
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#else
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#define write_all_windows() __asm __volatile("flushw" : : )
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#define write_user_windows() __asm __volatile("flushw" : : )
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#endif
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void proc_trampoline __P((void));
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struct pcb;
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void snapshot __P((struct pcb *));
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struct frame *getfp __P((void));
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int xldcontrolb __P((caddr_t, struct pcb *));
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void copywords __P((const void *, void *, size_t));
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void qcopy __P((const void *, void *, size_t));
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void qzero __P((void *, size_t));
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void switchtoctx __P((int));
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/* locore2.c */
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void remrq __P((struct proc *));
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/* trap.c */
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void kill_user_windows __P((struct proc *));
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int rwindow_save __P((struct proc *));
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void child_return __P((void *));
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/* amd7930intr.s */
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void amd7930_trap __P((void));
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/* cons.c */
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int cnrom __P((void));
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/* zs.c */
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void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int)));
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#ifdef KGDB
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void zs_kgdb_init __P((void));
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#endif
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/* fb.c */
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void fb_unblank __P((void));
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/* kgdb_stub.c */
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#ifdef KGDB
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void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *));
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void kgdb_connect __P((int));
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void kgdb_panic __P((void));
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#endif
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/* iommu.c */
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void iommu_enter __P((u_int, u_int));
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void iommu_remove __P((u_int, u_int));
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/* emul.c */
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int fixalign __P((struct proc *, struct trapframe *));
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int emulinstr __P((vaddr_t, struct trapframe *));
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/*
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*
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* The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits
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* of the trap vector table. The next eight bits are supplied by the
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* hardware when the trap occurs, and the bottom four bits are always
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* zero (so that we can shove up to 16 bytes of executable code---exactly
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* four instructions---into each trap vector).
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*
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* The hardware allocates half the trap vectors to hardware and half to
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* software.
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*
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* Traps have priorities assigned (lower number => higher priority).
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*/
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struct trapvec {
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int tv_instr[8]; /* the eight instructions */
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};
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extern struct trapvec *trapbase; /* the 256 vectors */
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extern void wzero __P((void *, u_int));
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extern void wcopy __P((const void *, void *, u_int));
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#endif /* _KERNEL */
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#endif /* _CPU_H_ */
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