466 lines
14 KiB
C
466 lines
14 KiB
C
/* $NetBSD: psl.h,v 1.22 2003/03/22 06:34:28 nakayama Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)psl.h 8.1 (Berkeley) 6/11/93
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*/
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#ifndef PSR_IMPL
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/*
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* SPARC Process Status Register (in psl.h for hysterical raisins). This
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* doesn't exist on the V9.
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*
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* The picture in the Sun manuals looks like this:
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* 1 1
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* 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0
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* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
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* | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP |
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* | | |n z v c| |C|F| | |S|T| |
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* +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+
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*/
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#define PSR_IMPL 0xf0000000 /* implementation */
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#define PSR_VER 0x0f000000 /* version */
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#define PSR_ICC 0x00f00000 /* integer condition codes */
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#define PSR_N 0x00800000 /* negative */
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#define PSR_Z 0x00400000 /* zero */
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#define PSR_O 0x00200000 /* overflow */
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#define PSR_C 0x00100000 /* carry */
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#define PSR_EC 0x00002000 /* coprocessor enable */
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#define PSR_EF 0x00001000 /* FP enable */
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#define PSR_PIL 0x00000f00 /* interrupt level */
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#define PSR_S 0x00000080 /* supervisor (kernel) mode */
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#define PSR_PS 0x00000040 /* previous supervisor mode (traps) */
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#define PSR_ET 0x00000020 /* trap enable */
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#define PSR_CWP 0x0000001f /* current window pointer */
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#define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET"
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/* Interesting spl()s */
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#define PIL_SCSI 3
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#define PIL_FDSOFT 4
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#define PIL_AUSOFT 4
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#define PIL_BIO 5
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#define PIL_VIDEO 5
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#define PIL_TTY 6
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#define PIL_LPT 6
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#define PIL_NET 6
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#define PIL_IMP 7
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#define PIL_CLOCK 10
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#define PIL_FD 11
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#define PIL_SER 12
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#define PIL_AUD 13
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#define PIL_HIGH 15
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#define PIL_SCHED PIL_CLOCK
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#define PIL_LOCK PIL_HIGH
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/*
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* SPARC V9 CCR register
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*/
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#define ICC_C 0x01L
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#define ICC_V 0x02L
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#define ICC_Z 0x04L
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#define ICC_N 0x08L
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#define XCC_SHIFT 4
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#define XCC_C (ICC_C<<XCC_SHIFT)
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#define XCC_V (ICC_V<<XCC_SHIFT)
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#define XCC_Z (ICC_Z<<XCC_SHIFT)
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#define XCC_N (ICC_N<<XCC_SHIFT)
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/*
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* SPARC V9 PSTATE register (what replaces the PSR in V9)
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*
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* Here's the layout:
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*
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* 11 10 9 8 7 6 5 4 3 2 1 0
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* +------------------------------------------------------------+
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* | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG |
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* +------------------------------------------------------------+
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*/
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#define PSTATE_IG 0x800 /* enable spitfire interrupt globals */
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#define PSTATE_MG 0x400 /* enable spitfire MMU globals */
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#define PSTATE_CLE 0x200 /* current little endian */
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#define PSTATE_TLE 0x100 /* traps little endian */
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#define PSTATE_MM 0x0c0 /* memory model */
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#define PSTATE_MM_TSO 0x000 /* total store order */
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#define PSTATE_MM_PSO 0x040 /* partial store order */
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#define PSTATE_MM_RMO 0x080 /* Relaxed memory order */
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#define PSTATE_RED 0x020 /* RED state */
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#define PSTATE_PEF 0x010 /* enable floating point */
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#define PSTATE_AM 0x008 /* 32-bit address masking */
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#define PSTATE_PRIV 0x004 /* privileged mode */
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#define PSTATE_IE 0x002 /* interrupt enable */
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#define PSTATE_AG 0x001 /* enable alternate globals */
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#define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG"
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/*
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* 32-bit code requires TSO or at best PSO since that's what's supported on
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* SPARC V8 and earlier machines.
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*
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* 64-bit code sets the memory model in the ELF header.
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*
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* We're running kernel code in TSO for the moment so we don't need to worry
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* about possible memory barrier bugs.
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*/
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#ifdef __arch64__
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#define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV)
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#define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG)
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#define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_PRIV)
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#define PSTATE_INTR (PSTATE_KERN|PSTATE_IE)
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#define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE)
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#define PSTATE_USER (PSTATE_MM_RMO|PSTATE_IE)
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#else
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#define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV)
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#define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV|PSTATE_AG)
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#define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV)
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#define PSTATE_INTR (PSTATE_KERN|PSTATE_IE)
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#define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE)
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#define PSTATE_USER (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE)
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#endif
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/*
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* SPARC V9 TSTATE register
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*
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* 39 32 31 24 23 18 17 8 7 5 4 0
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* +-----+-----+-----+--------+---+-----+
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* | CCR | ASI | - | PSTATE | - | CWP |
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* +-----+-----+-----+--------+---+-----+
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*/
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#define TSTATE_CWP 0x01f
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#define TSTATE_PSTATE 0x6ff00
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#define TSTATE_PSTATE_SHIFT 8
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#define TSTATE_ASI 0xff000000LL
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#define TSTATE_ASI_SHIFT 24
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#define TSTATE_CCR 0xff00000000LL
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#define TSTATE_CCR_SHIFT 32
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#define PSRCC_TO_TSTATE(x) (((int64_t)(x)&PSR_ICC)<<(TSTATE_CCR_SHIFT-19))
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#define TSTATECCR_TO_PSR(x) (((x)&TSTATE_CCR)>>(TSTATE_CCR_SHIFT-19))
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/*
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* These are here to simplify life.
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*/
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#define TSTATE_IG (PSTATE_IG<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_MG (PSTATE_MG<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_CLE (PSTATE_CLE<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_TLE (PSTATE_TLE<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_MM (PSTATE_MM<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_MM_TSO (PSTATE_MM_TSO<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_MM_PSO (PSTATE_MM_PSO<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_MM_RMO (PSTATE_MM_RMO<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_RED (PSTATE_RED<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_PEF (PSTATE_PEF<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_AM (PSTATE_AM<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_PRIV (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_IE (PSTATE_IE<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_AG (PSTATE_AG<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG"
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#define TSTATE_KERN ((TSTATE_KERN)<<TSTATE_PSTATE_SHIFT)
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#define TSTATE_USER ((TSTATE_USER)<<TSTATE_PSTATE_SHIFT)
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/*
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* SPARC V9 VER version register.
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*
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* 63 48 47 32 31 24 23 16 15 8 7 5 4 0
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* +-------+------+------+-----+-------+---+--------+
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* | manuf | impl | mask | - | maxtl | - | maxwin |
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* +-------+------+------+-----+-------+---+--------+
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*
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*/
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#define VER_MANUF 0xffff000000000000LL
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#define VER_MANUF_SHIFT 48
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#define VER_IMPL 0x0000ffff00000000LL
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#define VER_IMPL_SHIFT 32
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#define VER_MASK 0x00000000ff000000LL
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#define VER_MASK_SHIFT 24
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#define VER_MAXTL 0x000000000000ff00LL
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#define VER_MAXTL_SHIFT 8
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#define VER_MAXWIN 0x000000000000001fLL
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/*
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* Here are a few things to help us transition between user and kernel mode:
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*/
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/* Memory models */
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#define KERN_MM PSTATE_MM_TSO
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#define USER_MM PSTATE_MM_RMO
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/*
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* Register window handlers. These point to generic routines that check the
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* stack pointer and then vector to the real handler. We could optimize this
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* if we could guarantee only 32-bit or 64-bit stacks.
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*/
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#define WSTATE_KERN 026
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#define WSTATE_USER 022
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#define CWP 0x01f
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/* 64-byte alignment -- this seems the best place to put this. */
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#define BLOCK_SIZE 64
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#define BLOCK_ALIGN 0x3f
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#if defined(_KERNEL) && !defined(_LOCORE)
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extern u_int64_t ver; /* Copy of v9 version register. We need to read this only once, in locore.s. */
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static __inline int getpstate __P((void));
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static __inline void setpstate __P((int));
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static __inline int getcwp __P((void));
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static __inline void setcwp __P((int));
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#ifndef SPLDEBUG
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static __inline void splx __P((int));
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#endif
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static __inline u_int64_t getver __P((void));
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/*
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* GCC pseudo-functions for manipulating privileged registers
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*/
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static __inline int getpstate()
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{
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int pstate;
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__asm __volatile("rdpr %%pstate,%0" : "=r" (pstate));
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return (pstate);
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}
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static __inline void setpstate(newpstate)
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int newpstate;
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{
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__asm __volatile("wrpr %0,0,%%pstate" : : "r" (newpstate));
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}
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static __inline int getcwp()
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{
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int cwp;
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__asm __volatile("rdpr %%cwp,%0" : "=r" (cwp));
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return (cwp);
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}
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static __inline void setcwp(newcwp)
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int newcwp;
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{
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__asm __volatile("wrpr %0,0,%%cwp" : : "r" (newcwp));
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}
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static __inline u_int64_t getver()
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{
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u_int64_t ver;
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__asm __volatile("rdpr %%ver,%0" : "=r" (ver));
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return (ver);
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}
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/*
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* GCC pseudo-functions for manipulating PIL
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*/
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#ifdef SPLDEBUG
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void prom_printf __P((const char *fmt, ...));
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extern int printspl;
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#define SPLPRINT(x) \
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{ \
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if (printspl) { \
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int i = 10000000; \
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prom_printf x ; \
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while (i--) \
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; \
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} \
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}
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#define SPL(name, newpil) \
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static __inline int name##X __P((const char*, int)); \
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static __inline int name##X(const char* file, int line) \
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{ \
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int oldpil; \
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__asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
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SPLPRINT(("{%s:%d %d=>%d}", file, line, oldpil, newpil)); \
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__asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \
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return (oldpil); \
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}
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/* A non-priority-decreasing version of SPL */
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#define SPLHOLD(name, newpil) \
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static __inline int name##X __P((const char*, int)); \
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static __inline int name##X(const char* file, int line) \
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{ \
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int oldpil; \
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__asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
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if (newpil <= oldpil) \
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return oldpil; \
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SPLPRINT(("{%s:%d %d->!d}", file, line, oldpil, newpil)); \
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__asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \
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return (oldpil); \
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}
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#else
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#define SPLPRINT(x)
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#define SPL(name, newpil) \
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static __inline int name __P((void)); \
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static __inline int name() \
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{ \
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int oldpil; \
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__asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
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__asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \
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return (oldpil); \
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}
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/* A non-priority-decreasing version of SPL */
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#define SPLHOLD(name, newpil) \
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static __inline int name __P((void)); \
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static __inline int name() \
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{ \
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int oldpil; \
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__asm __volatile("rdpr %%pil,%0" : "=r" (oldpil)); \
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if (newpil <= oldpil) \
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return oldpil; \
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__asm __volatile("wrpr %%g0,%0,%%pil" : : "n" (newpil)); \
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return (oldpil); \
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}
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#endif
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SPL(spl0, 0)
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SPL(spllowersoftclock, 1)
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SPLHOLD(splsoftint, 1)
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#define splsoftclock splsoftint
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#define splsoftnet splsoftint
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SPLHOLD(splsoftserial, 4)
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/* audio software interrupts are at software level 4 */
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SPLHOLD(splausoft, PIL_AUSOFT)
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/* floppy software interrupts are at software level 4 too */
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SPLHOLD(splfdsoft, PIL_FDSOFT)
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/* Block devices */
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SPLHOLD(splbio, PIL_BIO)
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/* network hardware interrupts are at level 6 */
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SPLHOLD(splnet, PIL_NET)
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/* tty input runs at software level 6 */
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SPLHOLD(spltty, PIL_TTY)
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/* parallel port runs at software level 6 */
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SPLHOLD(spllpt, PIL_LPT)
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/*
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* Memory allocation (must be as high as highest network, tty, or disk device)
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*/
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SPLHOLD(splvm, PIL_IMP)
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SPLHOLD(splclock, PIL_CLOCK)
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/* fd hardware interrupts are at level 11 */
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SPLHOLD(splfd, PIL_FD)
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/* zs hardware interrupts are at level 12 */
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SPLHOLD(splzs, PIL_SER)
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SPLHOLD(splserial, PIL_SER)
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/* audio hardware interrupts are at level 13 */
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SPLHOLD(splaudio, PIL_AUD)
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/* second sparc timer interrupts at level 14 */
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SPLHOLD(splstatclock, 14)
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SPLHOLD(splsched, PIL_SCHED)
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SPLHOLD(spllock, PIL_LOCK)
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SPLHOLD(splhigh, PIL_HIGH)
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/* splx does not have a return value */
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#ifdef SPLDEBUG
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#define spl0() spl0X(__FILE__, __LINE__)
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#define spllowersoftclock() spllowersoftclockX(__FILE__, __LINE__)
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#define splsoftint() splsoftintX(__FILE__, __LINE__)
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#define splsoftserial() splsoftserialX(__FILE__, __LINE__)
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#define splausoft() splausoftX(__FILE__, __LINE__)
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#define splfdsoft() splfdsoftX(__FILE__, __LINE__)
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#define splbio() splbioX(__FILE__, __LINE__)
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#define splnet() splnetX(__FILE__, __LINE__)
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#define spltty() splttyX(__FILE__, __LINE__)
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#define spllpt() spllptX(__FILE__, __LINE__)
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#define splvm() splvmX(__FILE__, __LINE__)
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#define splclock() splclockX(__FILE__, __LINE__)
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#define splfd() splfdX(__FILE__, __LINE__)
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#define splzs() splzsX(__FILE__, __LINE__)
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#define splserial() splzerialX(__FILE__, __LINE__)
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#define splaudio() splaudioX(__FILE__, __LINE__)
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#define splstatclock() splstatclockX(__FILE__, __LINE__)
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#define splsched() splschedX(__FILE__, __LINE__)
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#define spllock() spllockX(__FILE__, __LINE__)
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#define splhigh() splhighX(__FILE__, __LINE__)
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#define splx(x) splxX((x),__FILE__, __LINE__)
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static __inline void splxX __P((int, const char*, int));
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static __inline void splxX(newpil, file, line)
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int newpil;
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const char *file;
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int line;
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#else
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static __inline void splx(newpil)
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int newpil;
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#endif
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{
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#ifdef SPLDEBUG
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int pil;
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__asm __volatile("rdpr %%pil,%0" : "=r" (pil));
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SPLPRINT(("{%d->%d}", pil, newpil));
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#endif
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__asm __volatile("wrpr %%g0,%0,%%pil" : : "rn" (newpil));
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}
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#endif /* KERNEL && !_LOCORE */
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#endif /* PSR_IMPL */
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