527 lines
14 KiB
C
527 lines
14 KiB
C
/* $NetBSD: pci_machdep.c,v 1.35 2003/03/22 06:33:09 nakayama Exp $ */
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/*
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* Copyright (c) 1999, 2000 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* functions expected by the MI PCI code.
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*/
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#ifdef DEBUG
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#define SPDB_CONF 0x01
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#define SPDB_INTR 0x04
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#define SPDB_INTMAP 0x08
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#define SPDB_INTFIX 0x10
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#define SPDB_PROBE 0x20
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int sparc_pci_debug = 0x0;
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#define DPRINTF(l, s) do { if (sparc_pci_debug & l) printf s; } while (0)
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#else
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#define DPRINTF(l, s)
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#endif
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/time.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#define _SPARC_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <machine/openfirm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ofw/ofw_pci.h>
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#include <sparc64/dev/iommureg.h>
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#include <sparc64/dev/iommuvar.h>
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#include <sparc64/dev/psychoreg.h>
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#include <sparc64/dev/psychovar.h>
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/* this is a base to be copied */
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struct sparc_pci_chipset _sparc_pci_chipset = {
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NULL,
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};
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static pcitag_t
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ofpci_make_tag(pci_chipset_tag_t pc, int node, int b, int d, int f)
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{
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pcitag_t tag;
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tag = PCITAG_CREATE(node, b, d, f);
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/* Enable all the different spaces for this device */
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pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG,
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PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE|
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PCI_COMMAND_IO_ENABLE);
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return (tag);
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}
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/*
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* functions provided to the MI code.
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*/
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void
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pci_attach_hook(parent, self, pba)
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struct device *parent;
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struct device *self;
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struct pcibus_attach_args *pba;
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{
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}
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int
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pci_bus_maxdevs(pc, busno)
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pci_chipset_tag_t pc;
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int busno;
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{
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return 32;
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}
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pcitag_t
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pci_make_tag(pc, b, d, f)
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pci_chipset_tag_t pc;
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int b;
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int d;
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int f;
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{
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struct psycho_pbm *pp = pc->cookie;
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struct ofw_pci_register reg;
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pcitag_t tag;
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int (*valid) __P((void *));
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int busrange[2];
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int node, len;
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#ifdef DEBUG
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char name[80];
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bzero(name, sizeof(name));
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#endif
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/*
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* Refer to the PCI/CardBus bus node first.
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* It returns a tag if node is present and bus is valid.
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*/
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if (0 <= b && b < 256) {
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node = (*pp->pp_busnode)[b].node;
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valid = (*pp->pp_busnode)[b].valid;
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if (node != 0 && d == 0 &&
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(valid == NULL || (*valid)((*pp->pp_busnode)[b].arg)))
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return ofpci_make_tag(pc, node, b, d, f);
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}
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/*
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* Hunt for the node that corresponds to this device
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*
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* We could cache this info in an array in the parent
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* device... except then we have problems with devices
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* attached below pci-pci bridges, and we would need to
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* add special code to the pci-pci bridge to cache this
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* info.
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*/
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tag = PCITAG_CREATE(-1, b, d, f);
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node = pc->rootnode;
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/*
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* First make sure we're on the right bus. If our parent
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* has a bus-range property and we're not in the range,
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* then we're obviously on the wrong bus. So go up one
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* level.
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*/
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#ifdef DEBUG
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if (sparc_pci_debug & SPDB_PROBE) {
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OF_getprop(node, "name", &name, sizeof(name));
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printf("curnode %x %s\n", node, name);
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}
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#endif
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#if 0
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while ((OF_getprop(OF_parent(node), "bus-range", (void *)&busrange,
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sizeof(busrange)) == sizeof(busrange)) &&
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(b < busrange[0] || b > busrange[1])) {
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/* Out of range, go up one */
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node = OF_parent(node);
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#ifdef DEBUG
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if (sparc_pci_debug & SPDB_PROBE) {
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OF_getprop(node, "name", &name, sizeof(name));
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printf("going up to node %x %s\n", node, name);
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}
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#endif
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}
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#endif
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/*
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* Now traverse all peers until we find the node or we find
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* the right bridge.
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*
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* XXX We go up one and down one to make sure nobody's missed.
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* but this should not be necessary.
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*/
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for (node = ((node)); node; node = OF_peer(node)) {
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#ifdef DEBUG
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if (sparc_pci_debug & SPDB_PROBE) {
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OF_getprop(node, "name", &name, sizeof(name));
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printf("checking node %x %s\n", node, name);
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}
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#endif
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#if 1
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/*
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* Check for PCI-PCI bridges. If the device we want is
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* in the bus-range for that bridge, work our way down.
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*/
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while ((OF_getprop(node, "bus-range", (void *)&busrange,
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sizeof(busrange)) == sizeof(busrange)) &&
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(b >= busrange[0] && b <= busrange[1])) {
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/* Go down 1 level */
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node = OF_child(node);
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#ifdef DEBUG
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if (sparc_pci_debug & SPDB_PROBE) {
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OF_getprop(node, "name", &name, sizeof(name));
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printf("going down to node %x %s\n",
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node, name);
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}
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#endif
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}
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#endif
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/*
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* We only really need the first `reg' property.
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*
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* For simplicity, we'll query the `reg' when we
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* need it. Otherwise we could malloc() it, but
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* that gets more complicated.
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*/
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len = OF_getproplen(node, "reg");
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if (len < sizeof(reg))
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continue;
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if (OF_getprop(node, "reg", (void *)®, sizeof(reg)) != len)
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panic("pci_probe_bus: OF_getprop len botch");
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if (b != OFW_PCI_PHYS_HI_BUS(reg.phys_hi))
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continue;
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if (d != OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi))
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continue;
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if (f != OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi))
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continue;
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/* Got a match */
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tag = ofpci_make_tag(pc, node, b, d, f);
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return (tag);
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}
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/* No device found -- return a dead tag */
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return (tag);
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}
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void
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pci_decompose_tag(pc, tag, bp, dp, fp)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int *bp, *dp, *fp;
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{
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if (bp != NULL)
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*bp = PCITAG_BUS(tag);
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if (dp != NULL)
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*dp = PCITAG_DEV(tag);
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if (fp != NULL)
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*fp = PCITAG_FUN(tag);
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}
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int
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pci_enumerate_bus(struct pci_softc *sc,
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int (*match)(struct pci_attach_args *), struct pci_attach_args *pap)
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{
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struct ofw_pci_register reg;
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pci_chipset_tag_t pc = sc->sc_pc;
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pcitag_t tag;
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pcireg_t class, csr, bhlc, ic;
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int node, b, d, f, ret;
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int len, bus_frequency, lt, cl;
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char name[30];
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extern int pci_config_dump;
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if (sc->sc_bridgetag)
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node = PCITAG_NODE(*sc->sc_bridgetag);
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else
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node = pc->rootnode;
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len = OF_getproplen(node, "clock-frequency");
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if (len < sizeof(bus_frequency)) {
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DPRINTF(SPDB_PROBE,
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("pci_enumerate_bus: clock-frequency len %d too small\n",
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len));
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return 0;
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}
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if (OF_getprop(node, "clock-frequency", &bus_frequency,
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sizeof(bus_frequency)) != len) {
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DPRINTF(SPDB_PROBE,
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("pci_enumerate_bus: could not read clock-frequency\n"));
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return 0;
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}
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bus_frequency /= 1000000;
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/* Turn on parity for the bus. */
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tag = ofpci_make_tag(pc, node, sc->sc_bus, 0, 0);
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csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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csr |= PCI_COMMAND_PARITY_ENABLE;
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pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
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/*
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* Initialize the latency timer register.
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* The value 0x40 is from Solaris.
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*/
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bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
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bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
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bhlc |= 0x40 << PCI_LATTIMER_SHIFT;
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pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
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if (pci_config_dump) pci_conf_print(pc, tag, NULL);
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for (node = OF_child(node); node != 0 && node != -1;
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node = OF_peer(node)) {
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name[0] = name[29] = 0;
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OF_getprop(node, "name", name, sizeof(name));
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if (OF_getprop(node, "class-code", &class, sizeof(class)) !=
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sizeof(class))
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continue;
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if (OF_getprop(node, "reg", ®, sizeof(reg)) < sizeof(reg))
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panic("pci_enumerate_bus: \"%s\" regs too small", name);
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b = OFW_PCI_PHYS_HI_BUS(reg.phys_hi);
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d = OFW_PCI_PHYS_HI_DEVICE(reg.phys_hi);
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f = OFW_PCI_PHYS_HI_FUNCTION(reg.phys_hi);
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if (sc->sc_bus != b) {
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printf("%s: WARNING: incorrect bus # for \"%s\" "
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"(%d/%d/%d)\n", sc->sc_dev.dv_xname, name, b, d, f);
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continue;
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}
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tag = ofpci_make_tag(pc, node, b, d, f);
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/*
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* Turn on parity and fast-back-to-back for the device.
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*/
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csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
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if (csr & PCI_STATUS_BACKTOBACK_SUPPORT)
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csr |= PCI_COMMAND_BACKTOBACK_ENABLE;
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csr |= PCI_COMMAND_PARITY_ENABLE;
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pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
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/*
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* Initialize the latency timer register for busmaster
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* devices to work properly.
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* latency-timer = min-grant * bus-freq / 4 (from FreeBSD)
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* Also initialize the cache line size register.
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* Solaris anytime sets this register to the value 0x10.
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*/
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bhlc = pci_conf_read(pc, tag, PCI_BHLC_REG);
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ic = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
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lt = min(PCI_MIN_GNT(ic) * bus_frequency / 4, 255);
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if (lt == 0 || lt < PCI_LATTIMER(bhlc))
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lt = PCI_LATTIMER(bhlc);
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cl = PCI_CACHELINE(bhlc);
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if (cl == 0)
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cl = 0x10;
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bhlc &= ~((PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT) |
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(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT));
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bhlc |= (lt << PCI_LATTIMER_SHIFT) |
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(cl << PCI_CACHELINE_SHIFT);
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pci_conf_write(pc, tag, PCI_BHLC_REG, bhlc);
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ret = pci_probe_device(sc, tag, match, pap);
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if (match != NULL && ret != 0)
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return (ret);
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}
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return (0);
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}
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/* assume we are mapped little-endian/side-effect */
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pcireg_t
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pci_conf_read(pc, tag, reg)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int reg;
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{
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struct psycho_pbm *pp = pc->cookie;
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struct psycho_softc *sc = pp->pp_sc;
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pcireg_t val = (pcireg_t)~0;
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DPRINTF(SPDB_CONF, ("pci_conf_read: tag %lx reg %x ",
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(long)tag, reg));
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if (PCITAG_NODE(tag) != -1) {
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DPRINTF(SPDB_CONF, ("asi=%x addr=%qx (offset=%x) ...",
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sc->sc_configaddr._asi,
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(long long)(sc->sc_configaddr._ptr +
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PCITAG_OFFSET(tag) + reg),
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(int)PCITAG_OFFSET(tag) + reg));
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val = bus_space_read_4(sc->sc_configtag, sc->sc_configaddr,
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PCITAG_OFFSET(tag) + reg);
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}
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#ifdef DEBUG
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else DPRINTF(SPDB_CONF, ("pci_conf_read: bogus pcitag %x\n",
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(int)PCITAG_OFFSET(tag)));
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#endif
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DPRINTF(SPDB_CONF, (" returning %08x\n", (u_int)val));
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return (val);
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}
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void
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pci_conf_write(pc, tag, reg, data)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int reg;
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pcireg_t data;
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{
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struct psycho_pbm *pp = pc->cookie;
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struct psycho_softc *sc = pp->pp_sc;
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DPRINTF(SPDB_CONF, ("pci_conf_write: tag %lx; reg %x; data %x; ",
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(long)PCITAG_OFFSET(tag), reg, (int)data));
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DPRINTF(SPDB_CONF, ("asi = %x; readaddr = %qx (offset = %x)\n",
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sc->sc_configaddr._asi,
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(long long)(sc->sc_configaddr._ptr + PCITAG_OFFSET(tag) + reg),
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(int)PCITAG_OFFSET(tag) + reg));
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/* If we don't know it, just punt it. */
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if (PCITAG_NODE(tag) == -1) {
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DPRINTF(SPDB_CONF, ("pci_conf_write: bad addr"));
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return;
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}
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bus_space_write_4(sc->sc_configtag, sc->sc_configaddr,
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PCITAG_OFFSET(tag) + reg, data);
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}
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/*
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* interrupt mapping foo.
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* XXX: how does this deal with multiple interrupts for a device?
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*/
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int
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pci_intr_map(pa, ihp)
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struct pci_attach_args *pa;
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pci_intr_handle_t *ihp;
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{
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pcitag_t tag = pa->pa_tag;
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int interrupts;
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int len, node = PCITAG_NODE(tag);
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char devtype[30];
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len = OF_getproplen(node, "interrupts");
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if (len < sizeof(interrupts)) {
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DPRINTF(SPDB_INTMAP,
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("pci_intr_map: interrupts len %d too small\n", len));
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return (ENODEV);
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}
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if (OF_getprop(node, "interrupts", (void *)&interrupts,
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sizeof(interrupts)) != len) {
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DPRINTF(SPDB_INTMAP,
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("pci_intr_map: could not read interrupts\n"));
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return (ENODEV);
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}
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if (OF_mapintr(node, &interrupts, sizeof(interrupts),
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sizeof(interrupts)) < 0) {
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printf("OF_mapintr failed\n");
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}
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/* Try to find an IPL for this type of device. */
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if (OF_getprop(node, "device_type", &devtype, sizeof(devtype)) > 0) {
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for (len = 0; intrmap[len].in_class; len++)
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if (strcmp(intrmap[len].in_class, devtype) == 0) {
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interrupts |= INTLEVENCODE(intrmap[len].in_lev);
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break;
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}
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}
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/* XXXX -- we use the ino. What if there is a valid IGN? */
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*ihp = interrupts;
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return (0);
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}
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const char *
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pci_intr_string(pc, ih)
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pci_chipset_tag_t pc;
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pci_intr_handle_t ih;
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{
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static char str[16];
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DPRINTF(SPDB_INTR, ("pci_intr_string: ih %u", ih));
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sprintf(str, "ivec %x", ih);
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DPRINTF(SPDB_INTR, ("; returning %s\n", str));
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return (str);
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}
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const struct evcnt *
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pci_intr_evcnt(pc, ih)
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pci_chipset_tag_t pc;
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pci_intr_handle_t ih;
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{
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/* XXX for now, no evcnt parent reported */
|
|
return NULL;
|
|
}
|
|
|
|
void *
|
|
pci_intr_establish(pc, ih, level, func, arg)
|
|
pci_chipset_tag_t pc;
|
|
pci_intr_handle_t ih;
|
|
int level;
|
|
int (*func) __P((void *));
|
|
void *arg;
|
|
{
|
|
void *cookie;
|
|
struct psycho_pbm *pp = (struct psycho_pbm *)pc->cookie;
|
|
|
|
DPRINTF(SPDB_INTR, ("pci_intr_establish: ih %lu; level %d", (u_long)ih, level));
|
|
cookie = bus_intr_establish(pp->pp_memt, ih, level, func, arg);
|
|
|
|
DPRINTF(SPDB_INTR, ("; returning handle %p\n", cookie));
|
|
return (cookie);
|
|
}
|
|
|
|
void
|
|
pci_intr_disestablish(pc, cookie)
|
|
pci_chipset_tag_t pc;
|
|
void *cookie;
|
|
{
|
|
|
|
DPRINTF(SPDB_INTR, ("pci_intr_disestablish: cookie %p\n", cookie));
|
|
|
|
/* XXX */
|
|
panic("can't disestablish PCI interrupts yet");
|
|
}
|