130 lines
4.3 KiB
C
130 lines
4.3 KiB
C
/* $NetBSD: sbd.h,v 1.2 2008/04/28 20:23:18 martin Exp $ */
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/*-
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* Copyright (c) 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _EWS4800MIPS_SBD_H_
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#define _EWS4800MIPS_SBD_H_
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/* System board model independ definition */
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struct sbdinfo {
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uint32_t machine :16;
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uint32_t model :16;
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uint32_t mmu :1;
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uint32_t cache :1;
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uint32_t panel :2;
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uint32_t padding1 :12;
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uint32_t fdd :8;
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uint32_t kb :8;
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uint32_t cpu :4;
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uint32_t fpp :4;
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uint32_t fpa :4;
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uint32_t iop :4;
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uint32_t padding2 :16; /* ----350---- */
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uint32_t clock :32;
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char model_name[20];
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uint32_t padding3 :24;
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uint32_t ipl :8;
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uint32_t cpu_ex :32;
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uint32_t fpp_ex :32; /* ----360---- */
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uint32_t padding4 :16;
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uint32_t kbms :4;
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uint32_t sio :4;
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uint32_t battery :8;
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uint32_t scsi :32;
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} __attribute__((__packed__));
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enum sbd_machine_type {
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MACHINE_TR2 = 0x1017, /* EWS4800/350 */
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MACHINE_TR2A = 0x101f /* EWS4800/360 */
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};
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/* Model independent ROM entries */
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#define SBD_INFO ((struct sbdinfo *)0xbfc0fe00)
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#define ROM_ADDR 0xbfc00000
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#define ROM_SIZE 0x00080000
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/* ROM_DK_RW(unit|flag, sector, count, addr) */
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#define ROM_DK_RW ((int (*)(int, uint32_t, uint32_t, void *))0xbfc0ff30)
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#define ROM_DK_READ(u, s, c, a) ROM_DK_RW(u, s, c, a)
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#define ROM_DK_WRITE(u, s, c, a) ROM_DK_RW(u | 0x1000, s, c, a)
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/* int ROM_GETC(void) */
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#define ROM_GETC ((int (*)(void))0xbfc0ff50)
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/* void ROM_PUTC(xpixel, ypixel, c) */
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#define ROM_PUTC ((void (*)(int, int, int))0xbfc0ff60)
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/* ROM_FD_RW(unit | flag, cylinder << 16 | side << 8 | sector, count, addr) */
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#define ROM_FD_RW ((int (*)(int, uint32_t, uint32_t, void *))0xbfc0ff20)
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#define ROM_FD_READ(u, s, c, a) ROM_FD_RW(u, s, c, a)
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#define ROM_FD_WRITE(u, s, c, a) ROM_FD_RW(u | 0x1000, s, c, a)
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#define ROM_ETHER_IPL 0xbfc0ff40
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#define ROM_CGMT_READ 0xbfc0ff48
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#define ROM_PRINTF 0xbfc0ff58
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#define ROM_NETIPL 0xbfc0ff68
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#define ROM_MONITOR ((void (*)(void))0xbfc0ff08)
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#define ROM_CPUITF 0xbfc0ff00 /* machine check */
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#define ROM_SPP 0xbfc0ff70
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#define ROM_SPPBP 0xbfc0ff78
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#define ROM_FONT_WIDTH 12
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#define ROM_FONT_HEIGHT 24
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/* NVSRAM */
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#define NVSRAM_BOOTDEV_MIN 0
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#define NVSRAM_BOOTDEV_FLOPPYDISK 0
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#define NVSRAM_BOOTDEV_HARDDISK 2
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#define NVSRAM_BOOTDEV_CGMT 4
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#define NVSRAM_BOOTDEV_NETWORK 6
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#define NVSRAM_BOOTDEV_NETWORK_T_AND_D 8
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#define NVSRAM_BOOTDEV_MAX 8
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/* RAM */
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struct mainfo_type1 {
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uint32_t reserved:14,
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m8:2, m7:2, m6:2, m5:2, m4:2, m3:2, m2:2, m1:2, m0:2;
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};
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/* TR2, TR2A */
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struct mainfo_type2 {
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uint32_t m7:4, m6:4, m5:4, m4:4, m3:4, m2:4, m1:4, m0:4;
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};
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#define MA0_ADDR 0x00000000
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#define __M0_BANK0_ADDR 0x00000000
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#define __M0_BANK1_ADDR 0x04000000
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#define MA1_ADDR 0x08000000
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#define __M1_BANK0_ADDR 0x08000000
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#define __M1_BANK1_ADDR 0x0c000000
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#define MA2_ADDR 0x10000000
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#define __M2_BANK0_ADDR 0x10000000
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#define __M2_BANK1_ADDR 0x14000000
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#define TR2A_MA3_ADDR 0x20000000
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#define TR2_MA3_ADDR 0x38000000
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#endif /* !_EWS4800MIPS_SBD_H_ */
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