4e2cf3688b
the fmovecr constant table has the internal format of the constants. So, when changing the mantissa size by a non-multiple of 32 bits, we'd have to change this table, too. As all other code changes just chopped of the least significand 32bit word of the mantissa, we correct the mantissa size instead to (115 - 32 == 83) bits. fpu_fmovecr.c: put a safety belt in, to catch the next person who doesn't know this. fpu_int.c: in one place, the reduction of the mantissa size was overlooked. fpu_log.c: as the most significand 32bit word of the mantissa was changed back to the old format, change back the table indexing code, too. This should fix PR 11045.
121 lines
4.3 KiB
C
121 lines
4.3 KiB
C
/* $NetBSD: fpu_fmovecr.c,v 1.8 2000/09/22 19:47:59 is Exp $ */
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/*
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* Copyright (c) 1995 Ken Nakata
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)fpu_fmovecr.c 10/8/95
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <machine/frame.h>
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#include "fpu_emulate.h"
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/* XXX: quick consistency check */
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#if (FP_1 != 0x40000)
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Error you have to change this table when changing the mantissa size
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#endif
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static struct fpn constrom[] = {
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/* fp_class, fp_sign, fp_exp, fp_sticky, fp_mant[0] ... [2] */
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{ FPC_NUM, 0, 1, 0, { 0x6487e, 0xd5110b46, 0x11a80000 } },
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{ FPC_NUM, 0, -2, 0, { 0x4d104, 0xd427de7f, 0xbcc00000 } },
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{ FPC_NUM, 0, 1, 0, { 0x56fc2, 0xa2c515da, 0x54d00000 } },
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{ FPC_NUM, 0, 0, 0, { 0x5c551, 0xd94ae0bf, 0x85e00000 } },
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{ FPC_NUM, 0, -2, 0, { 0x6f2de, 0xc549b943, 0x8ca80000 } },
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{ FPC_ZERO, 0, 0, 0, { 0x0, 0x0, 0x0 } },
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{ FPC_NUM, 0, -1, 0, { 0x58b90, 0xbfbe8e7b, 0xcd600000 } },
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{ FPC_NUM, 0, 1, 0, { 0x49aec, 0x6eed5545, 0x60b80000 } },
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{ FPC_NUM, 0, 0, 0, { 0x40000, 0x0, 0x0 } },
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{ FPC_NUM, 0, 3, 0, { 0x50000, 0x0, 0x0 } },
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{ FPC_NUM, 0, 6, 0, { 0x64000, 0x0, 0x0 } },
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{ FPC_NUM, 0, 13, 0, { 0x4e200, 0x0, 0x0 } },
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{ FPC_NUM, 0, 26, 0, { 0x5f5e1, 0x0, 0x0 } },
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{ FPC_NUM, 0, 53, 0, { 0x470de, 0x4df82000, 0x0 } },
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{ FPC_NUM, 0, 106, 0, { 0x4ee2d, 0x6d415b85, 0xacf00000 } },
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{ FPC_NUM, 0, 212, 0, { 0x613c0, 0xfa4ffe7d, 0x36a80000 } },
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{ FPC_NUM, 0, 425, 0, { 0x49dd2, 0x3e4c074c, 0x67000000 } },
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{ FPC_NUM, 0, 850, 0, { 0x553f7, 0x5fdcefce, 0xf4700000 } },
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{ FPC_NUM, 0, 1700, 0, { 0x718cd, 0x5753074, 0x8e380000 } },
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{ FPC_NUM, 0, 3401, 0, { 0x64bb3, 0xac340ba8, 0x60b80000 } },
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{ FPC_NUM, 0, 6803, 0, { 0x4f459, 0xdaee29ea, 0xef280000 } },
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{ FPC_NUM, 0, 13606, 0, { 0x62302, 0x90145104, 0xbcd80000 } },
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};
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struct fpn *
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fpu_const(fp, offset)
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struct fpn *fp;
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u_int offset;
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{
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struct fpn *r;
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#ifdef DEBUG
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if (fp == NULL) {
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panic("fpu_const: NULL pointer passed\n");
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}
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#endif
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if (offset == 0) {
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r = &constrom[0];
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} else if (0xb <= offset && offset <= 0xe) {
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r = &constrom[offset - 0xb + 1];
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} else if (0x30 <= offset && offset <= 0x3f) {
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r = &constrom[offset - 0x30 + 6];
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} else {
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/* return 0.0 for anything else (incl. valid offset 0xf) */
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r = &constrom[5];
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}
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CPYFPN(fp, r);
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return fp;
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}
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int
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fpu_emul_fmovecr(fe, insn)
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struct fpemu *fe;
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struct instruction *insn;
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{
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int dstreg, offset;
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u_int *fpreg;
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dstreg = (insn->is_word1 >> 7) & 0x7;
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offset = insn->is_word1 & 0x7F;
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fpreg = &(fe->fe_fpframe->fpf_regs[0]);
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(void)fpu_const(&fe->fe_f3, offset);
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(void)fpu_upd_fpsr(fe, &fe->fe_f3);
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fpu_implode(fe, &fe->fe_f3, FTYPE_EXT, &fpreg[dstreg * 3]);
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#if DEBUG_FPE
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printf(" fpu_emul_fmovecr: result %08x,%08x,%08x to FP%d\n",
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fpreg[dstreg * 3], fpreg[dstreg * 3 + 1], fpreg[dstreg * 3 + 2],
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dstreg);
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#endif
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return 0;
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}
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