9065e731d6
- New versions of the drivers for the devices that really are IOMD
specific. The old arm32/mainbus drivers have either been rewritten
and are now child devices of the IOMD or they have been restructured
and split into generic drivers will IOMD specific attachments.
254 lines
5.2 KiB
ArmAsm
254 lines
5.2 KiB
ArmAsm
/* $NetBSD: iomd_iic.S,v 1.1 1997/10/14 11:16:36 mark Exp $ */
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/*
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* Copyright (c) 1994-1996 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* iic.s
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*
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* Low level routines to with IIC devices
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*
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* Created : 13/10/94
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*
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* Based of kate/display/iic.s
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*/
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <arm32/iomd/iomdreg.h>
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#define IIC_BITDELAY 10
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sp .req r13
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lr .req r14
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pc .req r15
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.text
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.align 0
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ENTRY(iic_set_state)
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/*
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* Parameters
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* r0 - IIC data bit
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* r1 - IIC clock bit
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*/
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/* Store temporary register */
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/* stmfd sp!, {r4}*/
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/*
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* Mask the data and clock bits
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* Since these routines are only called from iiccontrol.c this is not
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* really needed
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*/
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and r0, r0, #0x00000001
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and r1, r1, #0x00000001
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/* Get address of IOMD control register */
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mov r2, #(IOMD_BASE)
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/* Get the current CPSR */
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/* mrs r4, cpsr_all
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orr r3, r4, #(I32_bit | F32_bit)
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msr cpsr_all, r3
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*/
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IRQdisable
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/* Get current value of control register */
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ldrb r3, [r2, #(IOMD_IOCR << 2)]
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/* Preserve non-IIC bits */
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bic r3, r3, #0x00000003
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#ifdef RC7500
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and r3, r3, #0x000000ff
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#else
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/* orr r3, r3, #0x000000c0*/
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#endif
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/* Set the IIC clock and data bits */
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orr r3, r3, r0
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orr r3, r3, r1, lsl #1
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/* Store the new value of control register */
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strb r3, [r2, #(IOMD_IOCR << 2)]
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/* Restore CPSR state */
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/* msr cpsr_all, r4 */
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IRQenable
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/* Restore temporary register */
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/* ldmfd sp!, {r4} */
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/* Pause a bit */
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mov r0, #(IIC_BITDELAY)
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/* Exit via iic_delay routine */
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b _iic_delay
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ENTRY(iic_set_state_and_ack)
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/*
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* Parameters
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* r0 - IIC data bit
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* r1 - IIC clock bit
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*/
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/* Store temporary register */
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/* stmfd sp!, {r4} */
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/*
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* Mask the data and clock bits
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* Since these routines are only called from iiccontrol.c this is not
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* really needed
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*/
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and r0, r0, #0x00000001
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and r1, r1, #0x00000001
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/* Get address of IOMD control register */
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mov r2, #(IOMD_BASE)
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/* Get the current CPSR */
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/* mrs r4, cpsr_all
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orr r3, r4, #(I32_bit | F32_bit)
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msr cpsr_all, r3
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*/
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IRQdisable
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/* Get current value of control register */
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ldrb r3, [r2, #(IOMD_IOCR << 2)]
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/* Preserve non-IIC bits */
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bic r3, r3, #0x00000003
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#ifdef RC7500
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and r3, r3, #0x000000ff
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#else
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/* orr r3, r3, #0x000000c0*/
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#endif
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/* Set the IIC clock and data bits */
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orr r3, r3, r0
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orr r3, r3, r1, lsl #1
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/* Store the new value of control register */
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strb r3, [r2, #(IOMD_IOCR << 2)]
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Liic_set_state_and_ack_loop:
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ldrb r3, [r2, #(IOMD_IOCR << 2)]
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tst r3, #0x00000002
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beq Liic_set_state_and_ack_loop
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/* Restore CPSR state */
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/* msr cpsr_all, r4 */
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IRQenable
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/* Restore temporary register */
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/* ldmfd sp!, {r4} */
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/* Pause a bit */
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mov r0, #(IIC_BITDELAY)
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/* Exit via iic_delay routine */
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b _iic_delay
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ENTRY(iic_delay)
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/*
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* Parameters
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* r0 - time to wait
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*/
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/* Load address of IOMD */
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mov r2, #(IOMD_BASE)
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/* Latch current value of timer 1 */
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strb r2, [r2, #(IOMD_T0LATCH << 2)]
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/* Get the latched value */
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ldrb r1, [r2, #(IOMD_T0LOW << 2)]
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/* Loop until timer reaches end value */
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Liic_delay_loop:
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/* Latch the current value of timer1 */
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strb r2, [r2, #(IOMD_T0LATCH << 2)]
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/* Get the latched value */
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ldrb r3, [r2, #(IOMD_T0LOW << 2)]
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/* Loop until timer reached expected value */
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teq r3, r1
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movne r1, r3
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beq Liic_delay_loop
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subs r0, r0, #0x00000001
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bne Liic_delay_loop
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/* Exit */
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mov pc, lr
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ENTRY(iic_getstate)
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/* Load address of IOMD */
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mov r2, #(IOMD_BASE)
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/* Read IOCR */
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ldrb r0, [r2, #(IOMD_IOCR << 2)]
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mov pc, lr
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/* End of iomd_iic.S */
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