54 lines
2.3 KiB
C
54 lines
2.3 KiB
C
/* $NetBSD: dmac_0266.h,v 1.1 1999/12/09 14:53:04 tsutsui Exp $ */
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/*-
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* Copyright (C) 1999 Izumi Tsutsui. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* DMAC 266 register definition */
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struct dma_regs {
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u_int32_t ctl; /* Control Register */
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#define DC_CTL_RST 0x04 /* Soft Reset */
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#define DC_CTL_MOD 0x02 /* set transfer dir */
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#define DC_CTL_ENB 0x01 /* set Enable */
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u_int32_t stat; /* Status Register */
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#define DC_ST_TCZ 0x10 /* Transfer Count Zero */
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#define DC_ST_INT 0x08 /* Interrupt */
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#define DC_ST_MOD 0x02 /* monitor transfer dir */
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#define DC_ST_ENB 0x01 /* monitor Enable */
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u_int32_t tcnt; /* transfer counter */
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u_int32_t tag; /* Tag Register */
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u_int32_t offset; /* Offset Register */
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u_int32_t mapent; /* Map entry Register */
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};
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#define DMAC_WAIT __asm __volatile ("nop; nop; nop; nop; nop; nop")
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#define DMAC_SEG_SIZE 0x1000 /* 4kbyte per DMA segment */
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#define DMAC_SEG_OFFSET 0x0fff
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#define DMAC_SEG_SHIFT 12
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