88 lines
2.4 KiB
ArmAsm
88 lines
2.4 KiB
ArmAsm
/* $NetBSD: locore.S,v 1.2 1999/12/22 05:54:41 tsubai Exp $ */
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/*-
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* Copyright (C) 1999 Tsubai Masanari. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <mips/asm.h>
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#include <mips/cpuregs.h>
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.set noreorder
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.text
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.align 2
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.globl _start
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_start:
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bal 1f
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nop
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1:
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la t0, 1b
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beq t0, ra, skip
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nop
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/* relocate myself */
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subu t0, ra, (1b - _start) # load address
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la t1, _start
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la t2, _edata
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2:
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lw t3, 0(t0)
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nop
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sw t3, 0(t1)
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addu t0, t0, 4
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addu t1, t1, 4
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bne t1, t2, 2b
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nop
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skip:
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j boot
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nop
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/*
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* void mips1_flushicache(addr, len)
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*/
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.globl mips1_flushicache
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mips1_flushicache:
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mfc0 v0, MIPS_COP_0_STATUS # save SR
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mtc0 zero, MIPS_COP_0_STATUS # disable interrupts
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la v1, 1f
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or v1, MIPS_KSEG1_START # run uncached
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j v1
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nop
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1:
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li v1, MIPS_SR_ISOL_CACHES | MIPS_SR_SWAP_CACHES
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mtc0 v1, MIPS_COP_0_STATUS
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nop
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addu a1, a1, a0 # compute ending address
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2:
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sb zero, -4(a0)
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bne a0, a1, 2b
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addu a0, a0, 4
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mtc0 v0, MIPS_COP_0_STATUS # enable interrupts
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j ra # return and run cached
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nop
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