121 lines
3.7 KiB
C
121 lines
3.7 KiB
C
/* $NetBSD: iocvar.h,v 1.2 2002/03/24 23:37:44 bjh21 Exp $ */
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/*-
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* Copyright (c) 1998, 1999 Ben Harris
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* iocvar.h - aspects of the IOC driver that are visible to the world.
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*/
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#ifndef _ARM26_IOCVAR_H
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#define _ARM26_IOCVAR_H
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#include <machine/irq.h>
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/* Structure passed to children of an IOC */
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struct ioc_attach_args {
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/* Means of accessing the device at various speeds */
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bus_space_tag_t ioc_fast_t;
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bus_space_handle_t ioc_fast_h;
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bus_space_tag_t ioc_medium_t;
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bus_space_handle_t ioc_medium_h;
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bus_space_tag_t ioc_slow_t;
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bus_space_handle_t ioc_slow_h;
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bus_space_tag_t ioc_sync_t;
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bus_space_handle_t ioc_sync_h;
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int ioc_bank; /* only for ioc_print */
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int ioc_offset;
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};
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struct ioc_softc {
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struct device sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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struct irq_handler *sc_clkirq;
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struct evcnt sc_clkev;
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struct irq_handler *sc_sclkirq;
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struct evcnt sc_sclkev;
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u_int8_t sc_ctl;
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};
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extern struct device *the_ioc;
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/* Public IOC functions */
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extern int ioc_irq_status(int);
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extern void ioc_irq_waitfor(int);
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extern void ioc_irq_clear(int);
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extern u_int32_t ioc_irq_status_full(void);
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extern void ioc_irq_setmask(u_int32_t);
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extern void ioc_fiq_setmask(u_int32_t);
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extern void ioc_counter_start(struct device *, int, int);
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extern void ioc_initclocks(struct device *);
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extern void ioc_setstatclockrate(struct device *, int);
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extern void ioc_microtime(struct device *, struct timeval *);
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/*
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* Control Register
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*/
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/*
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* ioc_ctl_{read,write}
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*
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* Functions to manipulate the IOC control register. The bottom six
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* bits of the control register map to bidirectional pins on the chip.
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* The output circuits are open-drain, so a pin is made an input by
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* writing '1' to it.
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*/
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static inline u_int
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ioc_ctl_read(struct device *self)
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{
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struct ioc_softc *sc = (void *)self;
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return bus_space_read_1(sc->sc_bst, sc->sc_bsh, IOC_CTL);
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}
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static inline void
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ioc_ctl_write(struct device *self, u_int value, u_int mask)
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{
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struct ioc_softc *sc = (void *)self;
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int s;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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s = splhigh();
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sc->sc_ctl = (sc->sc_ctl & ~mask) | (value & mask);
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bus_space_barrier(bst, bsh, IOC_CTL, 1, BUS_BARRIER_WRITE);
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bus_space_write_1(bst, bsh, IOC_CTL, sc->sc_ctl);
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bus_space_barrier(bst, bsh, IOC_CTL, 1, BUS_BARRIER_WRITE);
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splx(s);
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}
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#endif
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