595 lines
16 KiB
ArmAsm
595 lines
16 KiB
ArmAsm
/* $NetBSD: isa_irq.S,v 1.7 1999/10/26 06:53:43 cgd Exp $ */
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/*
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* Copyright 1997
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* Digital Equipment Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and
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* copied only in accordance with the following terms and conditions.
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* Subject to these conditions, you may download, copy, install,
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* use, modify and distribute this software in source and/or binary
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* form. No title or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce
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* and retain this copyright notice and list of conditions as
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* they appear in the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or logo of
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* Digital Equipment Corporation. Neither the "Digital Equipment
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* Corporation" name nor any trademark or logo of Digital Equipment
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* Corporation may be used to endorse or promote products derived
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* from this software without the prior written permission of
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* Digital Equipment Corporation.
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*
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* 3) This software is provided "AS-IS" and any express or implied
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* warranties, including but not limited to, any implied warranties
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* of merchantability, fitness for a particular purpose, or
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* non-infringement are disclaimed. In no event shall DIGITAL be
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* liable for any damages whatsoever, and in particular, DIGITAL
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* shall not be liable for special, indirect, consequential, or
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* incidental damages or damages for lost profits, loss of
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* revenue or loss of use, whether such damages arise in contract,
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* negligence, tort, under statute, in equity, at law or otherwise,
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* even if advised of the possibility of such damage.
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*/
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/*
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* Copyright (c) 1994-1998 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from: irq.S
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*
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* Low level irq and fiq handlers
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*
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* Created : 27/09/94
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*/
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#include "opt_irqstats.h"
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#include "assym.h"
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#include <machine/asm.h>
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#include <machine/cpu.h>
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#include <machine/frame.h>
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#include <dev/isa/isareg.h>
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#include <arm32/isa/icu.h>
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#include <machine/irqhandler.h>
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.text
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.align 0
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/*
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*
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* irq_entry
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*
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* Main entry point for the IRQ vector
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*
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* This function reads the irq request bits in the IOMD registers
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* IRQRQA, IRQRQB and DMARQ
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* It then calls an installed handler for each bit that is set.
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* The function stray_irqhandler is called if a handler is not defined
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* for a particular interrupt.
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* If a interrupt handler is found then it is called with r0 containing
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* the argument defined in the handler structure. If the field ih_arg
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* is zero then a pointer to the IRQ frame on the stack is passed instead.
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*/
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Ldisabled_mask:
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.word _C_LABEL(disabled_mask)
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Lcurrent_spl_level:
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.word _C_LABEL(current_spl_level)
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Lcurrent_intr_depth:
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.word _C_LABEL(current_intr_depth)
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Lvam_io_data:
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.word _C_LABEL(isa_io_bs_tag)
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Lspl_masks:
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.word _C_LABEL(spl_masks)
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/*
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* Register usage
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*
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* r6 - Address of current handler
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* r7 - Pointer to handler pointer list
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* r8 - Current IRQ requests.
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* r9 - Used to count through possible IRQ bits.
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* r10 - Base address of IOMD
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*/
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/* Some documentation is in isa_machdep.c */
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ASENTRY_NP(irq_entry)
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sub lr, lr, #0x00000004 /* Adjust the lr */
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PUSHFRAMEINSVC /* Push an interrupt frame */
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/* Load r8 with the ISA 8259 irqs */
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/* r8 <- irq's pending [15:0] */
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/* address of 8259 #1 */
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ldr r0, Lvam_io_data
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ldr r0, [r0]
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ldrb r8, [r0, #IO_ICU1] /* ocw3 = irr */
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/* clear the IRR bits that are currently masked. */
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ldr r2, Li8259_mask
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ldr r2, [r2]
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mvn r2, r2 /* disabled -> enabled */
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/* address of 8259 #2 */
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tst r2, #(1 << IRQ_SLAVE) /* if slave is enabled */
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tstne r8, #(1 << IRQ_SLAVE) /* anything from slave? */
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ldrneb r1, [r0, #IO_ICU2] /* ocw3 = irr */
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orrne r8, r8, r1, lsl #8
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and r8, r8, r2 /* clear disabled */
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/* clear IRQ 2, which is only used for slave 8259 */
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bic r8, r8, #(1 << IRQ_SLAVE)
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/*
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* Note that we have entered the IRQ handler.
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* We are in SVC mode so we cannot use the processor mode
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* to determine if we are in an IRQ. Instead we will count the
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* each time the interrupt handler is nested.
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*/
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ldr r0, Lcurrent_intr_depth
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ldr r1, [r0]
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add r1, r1, #1
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str r1, [r0]
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/* Block the current requested interrupts */
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ldr r1, Ldisabled_mask
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ldr r0, [r1]
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stmfd sp!, {r0}
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orr r0, r0, r8
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/*
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* Need to block all interrupts at the IPL or lower for
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* all asserted interrupts.
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* This basically emulates hardware interrupt priority levels.
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* Means we need to go through the interrupt mask and for
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* every asserted interrupt we need to mask out all other
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* interrupts at the same or lower IPL.
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* If only we could wait until the main loop but we need to sort
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* this out first so interrupts can be re-enabled.
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*
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* This would benefit from a special ffs type routine
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*/
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mov r9, #(_SPL_LEVELS - 1)
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ldr r7, Lspl_masks
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Lfind_highest_ipl:
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ldr r2, [r7, r9, lsl #2]
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tst r8, r2
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subeq r9, r9, #1
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beq Lfind_highest_ipl
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/* r9 = SPL level of highest priority interrupt */
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add r9, r9, #1
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ldr r2, [r7, r9, lsl #2]
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mvn r2, r2
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orr r0, r0, r2
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str r0, [r1]
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ldr r0, Lcurrent_spl_level
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ldr r1, [r0]
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str r9, [r0]
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stmfd sp!, {r1}
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/* Update the IOMD irq masks */
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bl _C_LABEL(irq_setmasks)
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mrs r0, cpsr_all /* Enable IRQ's */
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bic r0, r0, #I32_bit
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msr cpsr_all, r0
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ldr r7, [pc, #Lirqhandlers - . - 8]
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mov r9, #0x00000001
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irqloop:
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/* This would benefit from a special ffs type routine */
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tst r8, r9 /* Is a bit set ? */
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beq nextirq /* No ? try next bit */
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ldr r6, [r7] /* Get address of first handler structure */
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teq r6, #0x00000000 /* Do we have a handler */
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moveq r0, r8 /* IRQ requests as arg 0 */
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beq _C_LABEL(stray_irqhandler) /* call special handler */
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ldr r0, Lcnt
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ldr r1, [r0, #(V_INTR)]
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add r1, r1, #0x00000001
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str r1, [r0, #(V_INTR)]
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/*
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* XXX: Should stats be accumlated for every interrupt routine called
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* or for every physical interrupt that is serviced.
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*/
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#ifdef IRQSTATS
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ldr r0, Lintrcnt
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ldr r1, [r6, #(IH_NUM)]
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add r0, r0, r1, lsl #2
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ldr r1, [r0]
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add r1, r1, #0x00000001
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str r1, [r0]
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#endif /* IRQSTATS */
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irqchainloop:
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add lr, pc, #nextinchain - . - 8 /* return address */
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ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */
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teq r0, #0x00000000 /* If arg is zero pass stack frame */
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addeq r0, sp, #8 /* ... stack frame */
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ldr pc, [r6, #(IH_FUNC)] /* Call handler */
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nextinchain:
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teq r0, #0x00000001 /* Was the irq serviced ? */
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beq irqdone
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ldr r6, [r6, #(IH_NEXT)]
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teq r6, #0x00000000
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bne irqchainloop
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irqdone:
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nextirq:
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add r7, r7, #0x00000004 /* update pointer to handlers */
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mov r9, r9, lsl #1 /* move on to next bit */
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teq r9, #(1 << 16) /* done the last bit ? */
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bne irqloop /* no - loop back. */
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ldmfd sp!, {r2}
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ldr r1, Lcurrent_spl_level
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str r2, [r1]
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/* Restore previous disabled mask */
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ldmfd sp!, {r2}
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ldr r1, Ldisabled_mask
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str r2, [r1]
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bl _C_LABEL(irq_setmasks)
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bl _C_LABEL(dosoftints) /* Handle the soft interrupts */
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/* Manage AST's. Maybe this should be done as a soft interrupt ? */
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ldr r0, [sp] /* Get the SPSR from stack */
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and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the IRQ */
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teq r0, #(PSR_USR32_MODE)
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ldreq r0, Lastpending /* Do we have an AST pending ? */
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ldreq r1, [r0]
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teqeq r1, #0x00000001
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beq irqast /* call the AST handler */
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/* Kill IRQ's in preparation for exit */
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mrs r0, cpsr_all
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orr r0, r0, #(I32_bit)
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msr cpsr_all, r0
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/* Decrement the nest count */
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ldr r0, Lcurrent_intr_depth
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ldr r1, [r0]
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sub r1, r1, #1
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str r1, [r0]
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PULLFRAMEFROMSVCANDEXIT
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/* NOT REACHED */
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b . - 8
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/*
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* Ok, snag with current intr depth ...
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* If ast() calls mi_sleep() the current_intr_depth will not be
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* decremented until the process is woken up. This can result
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* in the system believing it is still in the interrupt handler.
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* If we are calling ast() then correct the current_intr_depth
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* before the call.
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*/
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irqast:
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mov r1, #0x00000000 /* Clear ast_pending */
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str r1, [r0]
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/* Kill IRQ's so we atomically decrement current_intr_depth */
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mrs r2, cpsr_all
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orr r3, r2, #(I32_bit)
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msr cpsr_all, r3
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/* Decrement the nest count */
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ldr r0, Lcurrent_intr_depth
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ldr r1, [r0]
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sub r1, r1, #1
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str r1, [r0]
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/* Restore IRQ's */
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msr cpsr_all, r2
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mov r0, sp
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bl _C_LABEL(ast)
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/* Kill IRQ's in preparation for exit */
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mrs r0, cpsr_all
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orr r0, r0, #(I32_bit)
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msr cpsr_all, r0
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PULLFRAMEFROMSVCANDEXIT
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/* NOT REACHED */
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b . - 8
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Lspl_mask:
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.word _C_LABEL(spl_mask) /* irq's allowed at current spl level */
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Lcurrent_mask:
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.word _C_LABEL(current_mask) /* irq's that are usable */
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ENTRY(irq_setmasks)
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/* Disable interrupts */
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mrs r3, cpsr_all
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orr r1, r3, #(I32_bit)
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msr cpsr_all, r1
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/* Calculate interrupt mask */
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ldr r1, Lcurrent_mask /* All the enabled interrupts */
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ldrh r1, [r1] /* get hardware bits of mask */
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/* .word 0xe0d110b0 */ /* hand-assembled ldrh r1, [r1] */
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ldr r2, Lspl_mask /* Block due to current spl level */
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ldr r2, [r2]
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and r1, r1, r2
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ldr r2, Ldisabled_mask /* Block due to active interrupts */
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ldr r2, [r2]
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bic r1, r1, r2
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/* since 8259's are so slow to access, this code does everything
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possible to avoid them */
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/* get current mask: these are the bits */
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ldr r0, Li8259_mask
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ldr r2, [r0]
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/* r2 = 0000.0000.0000.0000.ZZZZ.ZZZZ.ZZZZ.ZZZZ */
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/* see if there's anything enabled on 8259 #2 */
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tst r1, #0xff00
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biceq r1, r1, #(1 << IRQ_SLAVE) /* no, so disable it */
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orrne r1, r1, #(1 << IRQ_SLAVE) /* yes, so enable it */
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/* eq => r1 = 0000.0000.0000.0000.0000.0000.MMMM.M0MM
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ne => r1 = 0000.0000.0000.0000.MMMM.MMMM.MMMM.M1MM */
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/* 8259 bit high => disable */
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mvn r1, r1
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/* eq => r1 = 1111.1111.1111.1111.1111.1111.YYYY.Y1YY
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ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY
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(for each bit position Y = !M) */
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orreq r1, r2, r1, lsl #16
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/* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.ZZZZ.ZZZZ
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ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY */
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orreq r1, r1, #0x000000FF
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/* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.1111.1111
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ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY */
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and r1, r1, r1, lsr #16
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/* eq => r1 = 0000.0000.0000.0000.ZZZZ.ZZZZ.YYYY.Y1YY
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ne => r1 = 0000.0000.0000.0000.YYYY.YYYY.YYYY.Y0YY */
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/* if old = new, don't bother to set again.
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fast path to exit, since 8259's are so slow anyway */
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eors r2, r1, r2 /* which bits are different? */
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msreq cpsr_all, r3 /* no bits are different, return */
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moveq pc, lr
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/* have to set at least one of the 8259's, store new mask */
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str r1, [r0]
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ldr r0, Lvam_io_data
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ldr r0, [r0]
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/* see if there's any change for 8259 #1 (master) */
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tst r2, #0x00FF /* bottom 8 bits different? */
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strneb r1, [r0, #(IO_ICU1 + 1)] /* icu1 / ocw1 */
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/* anything for 8259 #2? */
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tst r2, #0xFF00
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mov r1, r1, lsr #8 /* next byte */
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strneb r1, [r0, #(IO_ICU2 + 1)] /* icu2 / ocw1 */
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/* Restore old cpsr and exit */
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msr cpsr_all, r3
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mov pc, lr
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Lcnt:
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.word _C_LABEL(uvmexp)
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Lintrcnt:
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.word _C_LABEL(intrcnt)
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Li8259_mask:
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.word _C_LABEL(i8259_mask)
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Lirqhandlers:
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.word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */
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Lastpending:
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.word _C_LABEL(astpending)
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#ifdef IRQSTATS
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/* These symbols are used by vmstat */
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.text
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.global _C_LABEL(_intrnames)
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_C_LABEL(_intrnames):
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.word _C_LABEL(intrnames)
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.data
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/* XXX fix */
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.globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt)
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_C_LABEL(intrnames):
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.asciz "interrupt 0 "
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.asciz "interrupt 1 "
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.asciz "interrupt 2 "
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.asciz "interrupt 3 "
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.asciz "interrupt 4 "
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.asciz "interrupt 5 "
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.asciz "interrupt 6 "
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.asciz "interrupt 7 "
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.asciz "interrupt 8 "
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.asciz "interrupt 9 "
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.asciz "interrupt 10 "
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.asciz "interrupt 11 "
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.asciz "interrupt 12 "
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.asciz "interrupt 13 "
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.asciz "interrupt 14 "
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.asciz "interrupt 15 "
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.asciz "interrupt 16 "
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.asciz "interrupt 17 "
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.asciz "interrupt 18 "
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.asciz "interrupt 19 "
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.asciz "interrupt 20 "
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.asciz "interrupt 21 "
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.asciz "interrupt 22 "
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.asciz "interrupt 23 "
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.asciz "interrupt 24 "
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.asciz "interrupt 25 "
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.asciz "interrupt 26 "
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.asciz "interrupt 27 "
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.asciz "interrupt 28 "
|
|
.asciz "interrupt 29 "
|
|
.asciz "interrupt 30 "
|
|
.asciz "interrupt 31 "
|
|
|
|
_C_LABEL(sintrnames):
|
|
.asciz "soft int 0 "
|
|
.asciz "soft int 1 "
|
|
.asciz "soft int 2 "
|
|
.asciz "soft int 3 "
|
|
.asciz "soft int 4 "
|
|
.asciz "soft int 5 "
|
|
.asciz "soft int 6 "
|
|
.asciz "soft int 7 "
|
|
.asciz "soft int 8 "
|
|
.asciz "soft int 9 "
|
|
.asciz "soft int 10 "
|
|
.asciz "soft int 11 "
|
|
.asciz "soft int 12 "
|
|
.asciz "soft int 13 "
|
|
.asciz "soft int 14 "
|
|
.asciz "soft int 15 "
|
|
.asciz "soft int 16 "
|
|
.asciz "soft int 17 "
|
|
.asciz "soft int 18 "
|
|
.asciz "soft int 19 "
|
|
.asciz "soft int 20 "
|
|
.asciz "soft int 21 "
|
|
.asciz "soft int 22 "
|
|
.asciz "soft int 23 "
|
|
.asciz "soft int 24 "
|
|
.asciz "soft int 25 "
|
|
.asciz "soft int 26 "
|
|
.asciz "soft int 27 "
|
|
.asciz "soft int 28 "
|
|
.asciz "soft int 29 "
|
|
.asciz "soft int 30 "
|
|
.asciz "soft int 31 "
|
|
_C_LABEL(eintrnames):
|
|
|
|
.bss
|
|
.align 0
|
|
_C_LABEL(intrcnt):
|
|
.space 32*4 /* XXX Should be linked to number of interrupts */
|
|
_C_LABEL(sintrcnt):
|
|
.space 32*4 /* XXX Should be linked to number of soft ints */
|
|
_C_LABEL(eintrcnt):
|
|
|
|
#else /* IRQSTATS */
|
|
/* Dummy entries to keep vmstat happy */
|
|
|
|
.text
|
|
.globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(eintrcnt)
|
|
_C_LABEL(intrnames):
|
|
.long 0
|
|
_C_LABEL(eintrnames):
|
|
|
|
_C_LABEL(intrcnt):
|
|
.long 0
|
|
_C_LABEL(eintrcnt):
|
|
#endif /* IRQSTATS */
|
|
|
|
/* FIQ code */
|
|
|
|
ENTRY(fiq_setregs)
|
|
mrs r2, cpsr_all
|
|
mov r3, r2
|
|
bic r2, r2, #(PSR_MODE)
|
|
orr r2, r2, #(PSR_FIQ32_MODE)
|
|
orr r2, r2, #(I32_bit | F32_bit) /* IRQs/FIQs definitely off */
|
|
msr cpsr_all, r2
|
|
|
|
ldr r8, [r0, #FH_R8] /* Update FIQ registers*/
|
|
ldr r9, [r0, #FH_R9]
|
|
ldr r10, [r0, #FH_R10]
|
|
ldr r11, [r0, #FH_R11]
|
|
ldr r12, [r0, #FH_R12]
|
|
ldr r13, [r0, #FH_R13]
|
|
|
|
msr cpsr_all, r3 /* Back to old mode */
|
|
|
|
mov pc, lr /* Exit */
|
|
|
|
ENTRY(fiq_getregs)
|
|
mrs r2, cpsr_all
|
|
mov r3, r2
|
|
bic r2, r2, #(PSR_MODE)
|
|
orr r2, r2, #(PSR_FIQ32_MODE)
|
|
orr r2, r2, #(I32_bit | F32_bit) /* IRQs/FIQs definitely off */
|
|
msr cpsr_all, r2
|
|
|
|
str r8, [r0, #FH_R8] /* Update FIQ registers*/
|
|
str r9, [r0, #FH_R9]
|
|
str r10, [r0, #FH_R10]
|
|
str r11, [r0, #FH_R11]
|
|
str r12, [r0, #FH_R12]
|
|
str r13, [r0, #FH_R13]
|
|
|
|
msr cpsr_all, r3 /* Back to old mode */
|
|
|
|
mov pc, lr /* Exit */
|
|
|
|
/* End of irq.S */
|