441 lines
11 KiB
C
441 lines
11 KiB
C
/* $NetBSD: picabus.c,v 1.11 2000/03/03 12:50:21 soda Exp $ */
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/* $OpenBSD: picabus.c,v 1.11 1999/01/11 05:11:10 millert Exp $ */
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/* NetBSD: tc.c,v 1.2 1995/03/08 00:39:05 cgd Exp */
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/*
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* Copyright (c) 1994, 1995 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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* Author: Per Fogelstrom. (Mips R4x00)
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <sys/device.h>
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#include <vm/vm.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/cpu.h>
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#include <machine/pio.h>
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#include <machine/autoconf.h>
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#include <arc/pica/pica.h>
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#include <arc/pica/rd94.h>
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#include <arc/arc/arctype.h>
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#include <arc/dev/dma.h>
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struct pica_softc {
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struct device sc_dv;
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struct abus sc_bus;
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struct pica_dev *sc_devs;
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};
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/* Definition of the driver for autoconfig. */
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int picamatch(struct device *, struct cfdata *, void *);
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void picaattach(struct device *, struct device *, void *);
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int picaprint(void *, const char *);
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struct cfattach pica_ca = {
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sizeof(struct pica_softc), picamatch, picaattach
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};
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extern struct cfdriver pica_cd;
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void pica_intr_establish __P((struct confargs *, int (*)(void *), void *));
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void pica_intr_disestablish __P((struct confargs *));
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caddr_t pica_cvtaddr __P((struct confargs *));
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int pica_matchname __P((struct confargs *, char *));
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int pica_iointr __P((unsigned int, struct clockframe *));
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int pica_clkintr __P((unsigned int, struct clockframe *));
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int rd94_iointr __P((unsigned int, struct clockframe *));
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int rd94_clkintr __P((unsigned int, struct clockframe *));
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intr_handler_t pica_clock_handler;
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/*
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* Interrupt dispatch table.
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*/
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struct pica_int_desc int_table[] = {
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{0, pica_intrnull, (void *)NULL, 0 }, /* 0 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 1 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 2 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 3 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 4 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 5 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 6 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 7 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 8 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 9 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 10 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 11 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 12 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 13 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 14 */
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{0, pica_intrnull, (void *)NULL, 0 }, /* 15 */
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};
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struct pica_dev {
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struct confargs ps_ca;
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u_int ps_mask;
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intr_handler_t ps_handler;
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caddr_t ps_base;
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};
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struct pica_dev acer_pica_61_cpu[] = {
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{{ "dallas_rtc",0, 0, },
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0, pica_intrnull, (void *)PICA_SYS_CLOCK, },
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{{ "lpt", 1, 0, },
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PICA_SYS_LB_IE_PAR1, pica_intrnull, (void *)PICA_SYS_PAR1, },
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{{ "fdc", 2, 0, },
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PICA_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)PICA_SYS_FLOPPY, },
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{{ NULL, 3, NULL, },
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0, pica_intrnull, (void *)NULL, },
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{{ NULL, 4, NULL, },
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0, pica_intrnull, (void *)NULL, },
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{{ "sonic", 5, 0, },
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PICA_SYS_LB_IE_SONIC, pica_intrnull, (void *)PICA_SYS_SONIC, },
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{{ "asc", 6, 0, },
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PICA_SYS_LB_IE_SCSI, pica_intrnull, (void *)PICA_SYS_SCSI, },
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{{ "pc", 7, 0, },
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PICA_SYS_LB_IE_KBD, pica_intrnull, (void *)PICA_SYS_KBD, },
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{{ "pms", 8, NULL, },
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PICA_SYS_LB_IE_MOUSE, pica_intrnull, (void *)PICA_SYS_KBD, },
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{{ "com", 9, 0, },
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PICA_SYS_LB_IE_COM1, pica_intrnull, (void *)PICA_SYS_COM1, },
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{{ "com", 10, 0, },
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PICA_SYS_LB_IE_COM2, pica_intrnull, (void *)PICA_SYS_COM2, },
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{{ NULL, -1, NULL, },
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0, NULL, (void *)NULL, },
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};
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struct pica_dev mips_magnum_r4000_cpu[] = {
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{{ "dallas_rtc",0, 0, },
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0, pica_intrnull, (void *)PICA_SYS_CLOCK, },
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{{ "lpt", 1, 0, },
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PICA_SYS_LB_IE_PAR1, pica_intrnull, (void *)PICA_SYS_PAR1, },
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{{ "fdc", 2, 0, },
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PICA_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)PICA_SYS_FLOPPY, },
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{{ NULL, 3, NULL, },
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0, pica_intrnull, (void *)NULL, },
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{{ "fb", 4, 0, },
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PICA_SYS_LB_IE_VIDEO, pica_intrnull, (void *)PICA_V_LOCAL_VIDEO, },
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{{ "sonic", 5, 0, },
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PICA_SYS_LB_IE_SONIC, pica_intrnull, (void *)PICA_SYS_SONIC, },
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{{ "asc", 6, 0, },
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PICA_SYS_LB_IE_SCSI, pica_intrnull, (void *)PICA_SYS_SCSI, },
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{{ "pckbd", 7, 0, },
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PICA_SYS_LB_IE_KBD, pica_intrnull, (void *)PICA_SYS_KBD, },
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{{ "pms", 8, NULL, },
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PICA_SYS_LB_IE_MOUSE, pica_intrnull, (void *)PICA_SYS_KBD, },
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{{ "com", 9, 0, },
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PICA_SYS_LB_IE_COM1, pica_intrnull, (void *)PICA_SYS_COM1, },
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{{ "com", 10, 0, },
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PICA_SYS_LB_IE_COM2, pica_intrnull, (void *)PICA_SYS_COM2, },
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{{ NULL, -1, NULL, },
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0, NULL, (void *)NULL, },
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};
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struct pica_dev nec_rd94_cpu[] = {
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{{ "dallas_rtc",0, 0, },
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0, pica_intrnull, (void *)RD94_SYS_CLOCK, },
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{{ "lpt", 1, 0, },
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RD94_SYS_LB_IE_PAR1, pica_intrnull, (void *)RD94_SYS_PAR1, },
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{{ "fdc", 2, 0, },
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RD94_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)RD94_SYS_FLOPPY, },
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{{ NULL, 3, NULL, },
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0, pica_intrnull, (void *)NULL, },
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{{ "sonic", 4, 0, },
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RD94_SYS_LB_IE_SONIC, pica_intrnull, (void *)RD94_SYS_SONIC, },
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{{ NULL, 5, NULL, },
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0, pica_intrnull, (void *)NULL, },
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{{ NULL, 6, NULL, },
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0, pica_intrnull, (void *)NULL, },
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{{ "pckbd", 7, 0, },
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RD94_SYS_LB_IE_KBD, pica_intrnull, (void *)RD94_SYS_KBD, },
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{{ "pms", 8, NULL, },
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RD94_SYS_LB_IE_MOUSE, pica_intrnull, (void *)RD94_SYS_KBD, },
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{{ "com", 9, 0, },
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RD94_SYS_LB_IE_COM1, pica_intrnull, (void *)RD94_SYS_COM1, },
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{{ "com", 10, 0, },
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RD94_SYS_LB_IE_COM2, pica_intrnull, (void *)RD94_SYS_COM2, },
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{{ NULL, -1, NULL, },
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0, NULL, (void *)NULL, },
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};
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struct pica_dev *pica_cpu_devs[] = {
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NULL, /* Unused */
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acer_pica_61_cpu, /* Acer PICA */
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mips_magnum_r4000_cpu, /* Mips MAGNUM R4000 */
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NULL,
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nec_rd94_cpu, /* NEC RISCstation 2250, etc. */
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};
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int npica_cpu_devs = sizeof pica_cpu_devs / sizeof pica_cpu_devs[0];
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int local_int_mask = 0; /* Local interrupt enable mask */
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int
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picamatch(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct confargs *ca = aux;
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/* Make sure that we're looking for a PICA. */
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if (strcmp(ca->ca_name, pica_cd.cd_name) != 0)
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return (0);
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/* Make sure that unit exists. */
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if (match->cf_unit != 0 ||
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cputype > npica_cpu_devs || pica_cpu_devs[cputype] == NULL)
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return (0);
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return (1);
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}
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void
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picaattach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct pica_softc *sc = (struct pica_softc *)self;
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struct confargs *nca;
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int i;
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printf("\n");
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/* keep our CPU device description handy */
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sc->sc_devs = pica_cpu_devs[cputype];
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/* set up interrupt handlers */
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switch (cputype) {
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case ACER_PICA_61:
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case MAGNUM:
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set_intr(MIPS_INT_MASK_1, pica_iointr, 2);
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break;
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case NEC_RD94:
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set_intr(MIPS_INT_MASK_1, rd94_iointr, 2);
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break;
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}
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sc->sc_bus.ab_dv = (struct device *)sc;
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sc->sc_bus.ab_type = BUS_PICA;
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sc->sc_bus.ab_intr_establish = pica_intr_establish;
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sc->sc_bus.ab_intr_disestablish = pica_intr_disestablish;
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sc->sc_bus.ab_cvtaddr = pica_cvtaddr;
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sc->sc_bus.ab_matchname = pica_matchname;
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/* Initialize PICA Dma */
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picaDmaInit();
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/* Try to configure each PICA attached device */
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for (i = 0; sc->sc_devs[i].ps_ca.ca_slot >= 0; i++) {
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if(sc->sc_devs[i].ps_ca.ca_name == NULL)
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continue; /* Empty slot */
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nca = &sc->sc_devs[i].ps_ca;
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nca->ca_bus = &sc->sc_bus;
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/* Tell the autoconfig machinery we've found the hardware. */
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config_found(self, nca, picaprint);
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}
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}
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int
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picaprint(aux, pnp)
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void *aux;
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const char *pnp;
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{
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struct confargs *ca = aux;
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if (pnp)
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printf("%s at %s", ca->ca_name, pnp);
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printf(" slot %d offset 0x%x", ca->ca_slot, ca->ca_offset);
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return (UNCONF);
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}
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caddr_t
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pica_cvtaddr(ca)
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struct confargs *ca;
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{
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struct pica_softc *sc = pica_cd.cd_devs[0];
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return(sc->sc_devs[ca->ca_slot].ps_base + ca->ca_offset);
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}
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void
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pica_intr_establish(ca, handler, val)
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struct confargs *ca;
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intr_handler_t handler;
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void *val;
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{
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struct pica_softc *sc = pica_cd.cd_devs[0];
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int slot;
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slot = ca->ca_slot;
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if(slot == 0) { /* Slot 0 is special, clock */
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pica_clock_handler = handler;
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switch (cputype) {
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case ACER_PICA_61:
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case MAGNUM:
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set_intr(MIPS_INT_MASK_4, pica_clkintr, 1);
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break;
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case NEC_RD94:
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set_intr(MIPS_INT_MASK_3, rd94_clkintr, 1);
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break;
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}
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}
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if(int_table[slot].int_mask != 0) {
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panic("pica intr already set");
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}
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else {
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int_table[slot].int_mask = sc->sc_devs[slot].ps_mask;;
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local_int_mask |= int_table[slot].int_mask;
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int_table[slot].int_hand = handler;
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int_table[slot].param = val;
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}
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switch (cputype) {
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case ACER_PICA_61:
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case MAGNUM:
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out16(PICA_SYS_LB_IE, local_int_mask);
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break;
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case NEC_RD94:
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/* XXX: I don't know why, but firmware does. */
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if (in32(0xe0000560) != 0)
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out16(RD94_SYS_LB_IE+2, local_int_mask);
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else
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out16(RD94_SYS_LB_IE, local_int_mask);
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break;
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}
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}
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void
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pica_intr_disestablish(ca)
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struct confargs *ca;
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{
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int slot;
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slot = ca->ca_slot;
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if(slot != 0) { /* Slot 0 is special, clock */
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local_int_mask &= ~int_table[slot].int_mask;
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int_table[slot].int_mask = 0;
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int_table[slot].int_hand = pica_intrnull;
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int_table[slot].param = (void *)NULL;
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}
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}
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int
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pica_matchname(ca, name)
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struct confargs *ca;
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char *name;
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{
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return (strcmp(name, ca->ca_name) == 0);
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}
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int
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pica_intrnull(val)
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void *val;
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{
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panic("uncaught PICA intr for slot %p", val);
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}
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/*
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* Handle pica i/o interrupt.
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*/
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int
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pica_iointr(mask, cf)
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unsigned mask;
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struct clockframe *cf;
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{
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int vector;
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while((vector = inb(PVIS) >> 2) != 0) {
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(*int_table[vector].int_hand)(int_table[vector].param);
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}
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return(~0); /* Dont reenable */
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}
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/*
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* Handle pica interval clock interrupt.
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*/
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int
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pica_clkintr(mask, cf)
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unsigned mask;
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struct clockframe *cf;
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{
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int temp;
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temp = inw(R4030_SYS_IT_STAT);
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(*pica_clock_handler)(cf);
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/* Re-enable clock interrupts */
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splx(MIPS_INT_MASK_4 | MIPS_SR_INT_IE);
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return(~MIPS_INT_MASK_4); /* Keep clock interrupts enabled */
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}
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/*
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* Handle NEC-RD94 i/o interrupt.
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*/
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int
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rd94_iointr(mask, cf)
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unsigned mask;
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struct clockframe *cf;
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{
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int vector;
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while((vector = inb(RD94_SYS_INTSTAT1) >> 2) != 0) {
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(*int_table[vector].int_hand)(int_table[vector].param);
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}
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return(~0); /* Dont reenable */
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}
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/*
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* Handle NEC-RD94 interval clock interrupt.
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*/
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int
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rd94_clkintr(mask, cf)
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unsigned mask;
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struct clockframe *cf;
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{
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int temp;
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temp = in32(RD94_SYS_INTSTAT3);
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(*pica_clock_handler)(cf);
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/* Re-enable clock interrupts */
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splx(MIPS_INT_MASK_3 | MIPS_SR_INT_IE);
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return(~MIPS_INT_MASK_3); /* Keep clock interrupts enabled */
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}
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