59474a8c82
SH-5, meet NetBSD. Let's hope this is the start of a long and fruitful relationship. :-) This code, funded by Wasabi Systems, adds initial support for the Hitachi SuperH(tm) SH-5 cpu architecture to NetBSD. At the present time, NetBSD/evbsh5 only runs on a SH-5 core simulator which has no simulated devices other than a simple console. However, it is good enough to get to the "root device: " prompt. Device driver support for Real SH-5 Hardware is in place, particularly for supporting the up-coming Cayman evaluation board, and should be quite easy to get running when the hardware is available. There is no in-tree toolchain for this port at this time. Gcc-current has rudimentary SH-5 support but it is known to be buggy. A working toolchain was obtained from SuperH to facilitate this port. Gcc-current will be fixed in due course. The SH-5 architecture is fully 64-bit capable, although NetBSD/evbsh5 has currently only been tested in 32-bit mode. It is bi-endian, via a boot- time option and it also has an "SHcompact" mode in which it will execute SH-[34] user-land instructions. For more information on the SH-5, see www.superh.com. Suffice to say it is *not* just another respin of the SH-[34].
145 lines
6.6 KiB
C
145 lines
6.6 KiB
C
/* $NetBSD: scifreg.h,v 1.1 2002/07/05 13:31:54 scw Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH5_SCIFREG_H
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#define _SH5_SCIFREG_H
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#define SCIF_REG_SCSMR2 0x00 /* 16: Serial mode register */
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#define SCIF_REG_SCBRR2 0x04 /* 8: Bit rate register */
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#define SCIF_REG_SCSCR2 0x08 /* 16: Serial control register */
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#define SCIF_REG_SCFTDR2 0x0c /* 8: Transmit FIFO data register */
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#define SCIF_REG_SCFSR2 0x10 /* 16: Serial status register */
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#define SCIF_REG_SCFRD2 0x14 /* 8: Receive FIFO data register */
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#define SCIF_REG_SCFCR2 0x18 /* 16: FIFO control register */
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#define SCIF_REG_SCFDR2 0x1c /* 16: FIFO data count register */
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#define SCIF_REG_SCSPTR2 0x20 /* 16: Serial port register */
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#define SCIF_REG_SCLSR2 0x24 /* 16: Line status register */
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#define SCIF_REG_SZ 0x30
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/*
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* Bit definitions for SCIF_REG_SCSMR2
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*/
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#define SCIF_SCSMR2_CKS_MASK 0x03 /* Clock Select 0 & 1 Mask */
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#define SCIF_SCSMR2_CKS_P1 0x00 /* Peripheral Clock / 1 */
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#define SCIF_SCSMR2_CKS_P4 0x01 /* Peripheral Clock / 4 */
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#define SCIF_SCSMR2_CKS_P16 0x02 /* Peripheral Clock / 16 */
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#define SCIF_SCSMR2_CKS_P64 0x03 /* Peripheral Clock / 64 */
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#define SCIF_SCSMR2_STOP1 0x00 /* 1 Stop Bit */
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#define SCIF_SCSMR2_STOP2 0x08 /* 2 Stop Bits */
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#define SCIF_SCSMR2_PAR_EVEN 0x00 /* Even parity */
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#define SCIF_SCSMR2_PAR_ODD 0x10 /* Odd parity */
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#define SCIF_SCSMR2_PAR_ENABLE 0x20 /* Parity enable */
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#define SCIF_SCSMR2_CHR_7 0x40 /* 7-bit character length */
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#define SCIF_SCSMR2_CHR_8 0x00 /* 8-bit character length */
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/*
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* Bit definitions for SCIF_REG_SCSCR2
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*/
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#define SCIF_SCSCR2_CKE_MASK 0x03 /* Clock enable mask */
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#define SCIF_SCSCR2_CKE_INT_IN 0x00 /* Internal clock/SCK2 pin ignored */
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#define SCIF_SCSCR2_CKE_INT_OUT 0x01 /* Internal clock/SCK2 clock output */
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#define SCIF_SCSCR2_CKE_EXT_IN 0x02 /* External clock/SCK2 clock input */
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#define SCIF_SCSCR2_CKE_EXT_IN16 0x03 /* External clock/SCK2 clock input/16 */
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#define SCIF_SCSCR2_REIE 0x08 /* Receive error interrupt enable */
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#define SCIF_SCSCR2_RE 0x10 /* Receive enable */
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#define SCIF_SCSCR2_TE 0x20 /* Transmit enable */
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#define SCIF_SCSCR2_RIE 0x40 /* Receive interrupt enable */
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#define SCIF_SCSCR2_TIE 0x80 /* Transmit interrupt enable */
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/*
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* Bit definitions for SCIF_REG_SCFSR2
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*/
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#define SCIF_SCFSR2_DR 0x01 /* Receive data ready */
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#define SCIF_SCFSR2_RDF 0x02 /* Receive FIFO data full */
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#define SCIF_SCFSR2_PER 0x04 /* Parity error */
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#define SCIF_SCFSR2_FER 0x08 /* Framing error */
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#define SCIF_SCFSR2_BRK 0x10 /* Break detect */
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#define SCIF_SCFSR2_TDFE 0x20 /* Transmit FIFO data empty */
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#define SCIF_SCFSR2_TEND 0x40 /* Transmit end */
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#define SCIF_SCFSR2_ER 0x80 /* Receive error */
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#define SCIF_SCFSR2_FER_MASK 0x0f /* Number of framing errors */
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#define SCIF_SCFSR2_FER_SHIFT 8
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#define SCIF_SCFSR2_PER_MASK 0x0f /* Number of parity errors */
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#define SCIF_SCFSR2_PER_SHIFT 12
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/*
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* Bit definitions for SCIF_REG_SCFCR2
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*/
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#define SCIF_SCFCR2_LOOP 0x01 /* Loopback test enable */
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#define SCIF_SCFCR2_RFRST 0x02 /* Receive FIFO data register reset */
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#define SCIF_SCFCR2_TFRST 0x04 /* Transmit FIFO data register reset */
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#define SCIF_SCFCR2_MCE 0x08 /* Modem control enable */
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#define SCIF_SCFCR2_TTRG_MASK 0x30 /* Transmit FIFO data number triggers */
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#define SCIF_SCFCR2_TTRG_8 0x00 /* Trigger on Tx FIFO remaining len 8 */
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#define SCIF_SCFCR2_TTRG_4 0x10 /* Trigger on Tx FIFO remaining len 4 */
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#define SCIF_SCFCR2_TTRG_2 0x20 /* Trigger on Tx FIFO remaining len 2 */
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#define SCIF_SCFCR2_TTRG_1 0x30 /* Trigger on Tx FIFO remaining len 1 */
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#define SCIF_SCFCR2_RTRG_MASK 0xc0 /* Receive FIFO data number triggers */
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#define SCIF_SCFCR2_RTRG_1 0x00 /* Trigger on Rx FIFO data length 1 */
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#define SCIF_SCFCR2_RTRG_4 0x40 /* Trigger on Rx FIFO data length 4 */
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#define SCIF_SCFCR2_RTRG_8 0x80 /* Trigger on Rx FIFO data length 8 */
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#define SCIF_SCFCR2_RTRG_14 0xc0 /* Trigger on Rx FIFO data length 14 */
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#define SCIF_SCFCR2_RSTRG(n) /* RTS2 output active trigger */ \
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(((n)==15) ? 0 : (((n)==1) ? 0x100 : (((n)/2)+0x700))
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/*
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* Bit definitions for SCIF_REG_SCFDR2
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*/
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#define SCIF_SCFDR2_R_MASK 0x0f /* Received data count */
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#define SCIF_SCFDR2_R_SHIFT 0
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#define SCIF_SCFDR2_T_MASK 0x0f /* Transmitted data count */
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#define SCIF_SCFDR2_T_SHIFT 8
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/*
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* Bit definitions for SCIF_REG_SCSPTR2
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*/
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#define SCIF_SCSPTR2_SPB2DT 0x01 /* Serial port break data */
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#define SCIF_SCSPTR2_SPB2IO 0x02 /* Serial port break I/O */
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#define SCIF_SCSPTR2_SCKDT 0x04 /* Serial port clock port data */
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#define SCIF_SCSPTR2_SCKIO 0x08 /* Serial port clock port I/O */
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#define SCIF_SCSPTR2_CTSDT 0x10 /* Serial port CTS port data */
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#define SCIF_SCSPTR2_CTSIO 0x20 /* Serial port CTS port I/O */
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#define SCIF_SCSPTR2_RTSDT 0x40 /* Serial port RTS port data */
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#define SCIF_SCSPTR2_RTSIO 0x80 /* Serial port RTS port I/O */
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/*
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* Bit definitions for SCIF_REG_SCLSR2
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*/
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#define SCIF_SCLSR2_ORER 0x01 /* Overrun error */
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#endif /* _SH5_SCIFREG_H */
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