119 lines
4.6 KiB
C
119 lines
4.6 KiB
C
/* $NetBSD: dmacreg.h,v 1.1 2005/01/29 11:37:18 scw Exp $ */
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/*-
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* Copyright (c) 2005 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH5_DMACREG_H
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#define _SH5_DMACREG_H
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#define DMAC_MODULE_ID 0x0183
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/*
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* Offsets to the register areas of dma controller.
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*/
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#define DMAC_COMMON 0x08
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#define DMAC_SAR(c) (0x10 + (0x28 * (c)))
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#define DMAC_DAR(c) (0x18 + (0x28 * (c)))
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#define DMAC_COUNT(c) (0x20 + (0x28 * (c)))
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#define DMAC_CTRL(c) (0x28 + (0x28 * (c)))
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#define DMAC_STATUS(c) (0x30 + (0x28 * (c)))
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#define DMAC_DMAEXG 0xc0
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#define DMAC_REG_SZ 0xc8
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#define DMAC_N_CHANNELS 4
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/*
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* Bit definitions for DMAC_COMMON
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*/
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#define DMAC_COMMON_PRIORITY_ROUND_ROBIN (1u << 0)
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#define DMAC_COMMON_MASTER_ENABLE (1u << 3)
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#define DMAC_COMMON_NMI_FLAG (1u << 4)
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#define DMAC_COMMON_ERROR_RESPONSE(c) (1u << (7 + (c)))
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#define DMAC_COMMON_ADDRESS_ALIGNMENT_ERROR(c) (1u << (11 + (c)))
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/*
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* Masks for DMAC_SAR/DMAC_DAR/DMAC_COUNT
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*/
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#define DMAC_SAR_MASK(a) ((a) & 0x00000000ffffffffull)
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#define DMAC_DAR_MASK(a) ((a) & 0x00000000ffffffffull)
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#define DMAC_COUNT_MASK(a) ((a) & 0x00000000ffffffffull)
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/*
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* Bit definitions for DMAC_CTRL
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*/
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#define DMAC_CTRL_TRANSFER_SIZE_MASK 0x0018
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#define DMAC_CTRL_TRANSFER_SIZE_1 0x0
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#define DMAC_CTRL_TRANSFER_SIZE_2 0x1
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#define DMAC_CTRL_TRANSFER_SIZE_4 0x2
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#define DMAC_CTRL_TRANSFER_SIZE_8 0x3
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#define DMAC_CTRL_TRANSFER_SIZE_16 0x4
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#define DMAC_CTRL_TRANSFER_SIZE_32 0x5
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#define DMAC_CTRL_SOURCE_INCREMENT_MASK 0x0018
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#define DMAC_CTRL_SOURCE_INCREMENT_INC 0x0000
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#define DMAC_CTRL_SOURCE_INCREMENT_DEC 0x0008
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#define DMAC_CTRL_SOURCE_INCREMENT_HOLD 0x0010
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#define DMAC_CTRL_DESTINATION_INCREMENT_MASK 0x0060
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#define DMAC_CTRL_DESTINATION_INCREMENT_INC 0x0000
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#define DMAC_CTRL_DESTINATION_INCREMENT_DEC 0x0020
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#define DMAC_CTRL_DESTINATION_INCREMENT_HOLD 0x0040
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#define DMAC_CTRL_RESOURCE_SELECT_MASK 0x0780
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#define DMAC_CTRL_RESOURCE_SELECT_AUTO 0x0000
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#define DMAC_CTRL_RESOURCE_SELECT_PERIPH_0 0x0080
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#define DMAC_CTRL_RESOURCE_SELECT_PERIPH_1 0x0100
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#define DMAC_CTRL_RESOURCE_SELECT_PERIPH_2 0x0180
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#define DMAC_CTRL_RESOURCE_SELECT_PERIPH_3 0x0200
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#define DMAC_CTRL_INTERRUPT_ENABLE (1u << 11)
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#define DMAC_CTRL_TRANSFER_ENABLE (1u << 12)
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/*
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* Bit definitions for DMAC_STATUS
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*/
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#define DMAC_STATUS_TRANSFER_END (1u << 0)
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#define DMAC_STATUS_ADDRESS_ALIGN_ERROR (1u << 1)
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/*
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* Bit definitions for DMAC_DMAEXG
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*/
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#define DMAC_DMAEXG_DACK_READWRITE(c) (1u << (c))
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#define DMAC_DMAEXG_DREQ_ATTRIBUTE(c) (1u << ((c) + 4)
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#define DMAC_DMAEXG_DRACK_ATTRIBUTE(c) (1u << ((c) + 8)
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#define DMAC_DMAEXG_DACK_ATTRIBUTE(c) (1u << ((c) + 12)
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#define DMAC_DMAEXG_REQUEST_MODE(c) (1u << ((c) + 16)
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#define DMAC_DMAEXG_REQUEST_QUEUE_DEPTH(c) (1u << ((c) + 20)
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#define DMAC_DMAEXG_REQUEST_QUEUE_CLEAR_ENABLE(c) (1u << ((c) + 24)
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#endif /* _SH5_DMACREG_H */
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