197 lines
7.7 KiB
C
197 lines
7.7 KiB
C
/* $NetBSD: beccreg.h,v 1.2 2003/04/05 04:18:26 briggs Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _BECCREG_H_
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#define _BECCREG_H_
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/*
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* Register definitions for the ADI Engineering Big Endian Companion
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* Chip for the Intel i80200.
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*/
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/* Revision codes */
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#define BECC_REV_V7 0x00 /* rev <= 7 */
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#define BECC_REV_V8 0x01 /* rev 8 */
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#define BECC_REV_V9 0x02 /* rev >= 9 */
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/* Memory Map */
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#define BECC_REG_BASE 0x04000000
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#define BECC_REG_SIZE 0x01000000 /* 16M */
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#define BECC_PCI_CONF_BASE 0x08000000
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#define BECC_PCI_CONF_SIZE 0x02000000 /* 32M */
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#define BECC_PCI_IO_BASE 0x0a000000
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#define BECC_PCI_IO_SIZE 0x02000000 /* 32M */
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#define BECC_PCI_MEM1_BASE 0x0c000000
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#define BECC_PCI_MEM1_SIZE 0x02000000 /* 32M */
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#define BECC_PCI_MEM2_BASE 0x0e000000
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#define BECC_PCI_MEM2_SIZE 0x02000000 /* 32M */
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#define BECC_SDRAM_BASE 0xc0000000
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/* Peripheral clock is 33.3MHz */
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#define BECC_PERIPH_CLOCK 33300000
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/* BECC registers; offsets from BECC_REG_BASE */
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#define BECC_PSISR 0x0000 /* PCI slave interrupt status */
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#define PSISR_SERR (1U << 4) /* system error */
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#define PSISR_PERR (1U << 9) /* parity error */
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#define PSISR_IFU (1U << 16) /* inbound FIFO uflow */
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#define PSISR_IFO (1U << 17) /* inbound FIFO oflow */
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#define PSISR_OFU (1U << 18) /* outbound FIFO uflow */
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#define PSISR_OFO (1U << 19) /* outbound FIFO oflow */
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#define BECC_PSTR0 0x0010 /* PCI slave translation window #0 */
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#define BECC_PSTR1 0x0018 /* PCI slave translation window #1 */
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#define PSTRx_ADDRMASK (3U << 25) /* address mask */
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#define PSTRx_BEE (1U << 0) /* big-endian enable */
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#define BECC_PSTR2 0x0020 /* PCI slave translation window #2 */
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#define PSTR2_ADDRMASK (0U) /* address mask (all SDRAM) */
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#define BECC_PMISR 0x0100 /* PCI master interrupt status */
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#define PMISR_PE (1U << 0) /* parity error */
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#define PMISR_TA (1U << 2) /* target abort */
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#define PMISR_MA (1U << 3) /* master abort */
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#define PMISR_IFU (1U << 16) /* inbound FIFO uflow */
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#define PMISR_IFO (1U << 17) /* inbound FIFO oflow */
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#define PMISR_OFU (1U << 18) /* outbound FIFO uflow */
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#define PMISR_OFO (1U << 19) /* outbound FIFO oflow */
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#define BECC_IDSEL_BIT 11 /* first device on PCI bus */
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#define BECC_POMR1 0x0110 /* PCI outbound memory window #1 */
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#define BECC_POMR2 0x0114 /* PCI outbound memory window #2 */
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#define POMRx_ADDRMASK 0xfe000000 /* address mask */
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#define POMRx_BEE (1U << 2) /* big-endian enable */
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#define POMRx_F32 (1U << 3) /* force 32-bit transfer */
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#define POMRx_BO(x) (x) /* busrt order (MBZ) */
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#define BECC_POMR3 0x0130 /* PCI outbound memory window #3 */
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#define POMR3_ADDRMASK 0xc0000000 /* address mask */
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#define BECC_POIR 0x0118 /* PCI outbound I/O window */
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#define POIR_ADDRMASK 0xfe000000 /* address mask */
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#define POIR_BEE (1U << 2) /* big-endian enable */
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#define BECC_POCR 0x0120 /* PCI outbound config window */
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#define POCR_BEE (1U << 2) /* big-endian enable */
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#define POCR_TYPE (1U << 0) /* for type 1 cycles */
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#define BECC_DMACR 0x0200 /* DMA control register */
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#define DMACR_CE (1U << 0) /* channel enable */
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#define BECC_DMASR 0x0204 /* DMA status register */
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#define DMASR_PEF (1U << 0) /* PCI parity error */
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#define DMASR_PTA (1U << 2) /* PCI target abort */
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#define DMASR_PMA (1U << 3) /* PCI master abort */
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#define DMASR_EOTI (1U << 8) /* end of transfer interrupt */
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#define DMASR_CA (1U << 10) /* channel active */
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#define DMASR_IFU (1U << 16) /* inbound FIFO uflow */
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#define DMASR_IFO (1U << 17) /* inbound FIFO oflow */
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#define DMASR_OFU (1U << 18) /* outbound FIFO uflow */
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#define DMASR_OFO (1U << 19) /* outbound FIFO oflow */
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#define BECC_DMAPCIAR 0x0210 /* DMA PCI address */
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#define BECC_DMALAR 0x021c /* DMA local address */
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#define BECC_DMABCR 0x0220 /* DMA byte count */
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#define BECC_DMADCR 0x0224 /* DMA descriptor control */
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#define DMADCR_F32 (1U << 6) /* force 32-bit */
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#define DMADCR_BEE (1U << 5) /* big-endian enable */
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#define DMADCR_PCICMD(x) (x) /* PCI command */
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#define PCICMD_MR 0x6 /* memory read */
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#define PCICMD_MRL 0xe /* memory read line */
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#define PCICMD_MRM 0xc /* memory read multiple */
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#define PCICMD_MW 0x7 /* memory write */
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#define BECC_TSCRA 0x0300 /* Timer status/control A */
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#define BECC_TSCRB 0x0320 /* Timer status/control B */
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#define TSCRx_TE (1U << 0) /* timer enable */
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#define TSCRx_CM (1U << 1) /* continuous mode */
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#define TSCRx_TIF (1U << 9) /* timer interrupt flag */
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#define BECC_TPRA 0x0304 /* Timer preload A */
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#define BECC_TPRB 0x0324 /* Timer preload B */
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#define BECC_TCVRA 0x0308 /* Timer current value A */
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#define BECC_TCVRB 0x0328 /* Timer current value B */
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#define BECC_ICSR 0x0400 /* Interrupt control/status */
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#define BECC_ICMR 0x0404 /* Interrupt mask */
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#define BECC_ICSTR 0x0408 /* Interrupt steer */
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#define ICU_SOFT 0 /* software interrupt */
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#define ICU_TIMERA 1 /* timer A */
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#define ICU_TIMERB 2 /* timer B */
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#define ICU_DIAGERR 7 /* diagnostic error */
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#define ICU_DMA_EOT 8 /* DMA end-of-transfer */
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#define ICU_DMA_PEF 9 /* DMA parity error */
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#define ICU_DMA_TA 10 /* DMA target abort */
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#define ICU_DMA_MA 11 /* DMA master abort */
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#define ICU_PCI_PERR 16 /* PCI parity error */
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#define ICU_PCI_SERR 19 /* PCI system error */
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#define ICU_PCI_POAPEI 20 /* PCI outbound ATU parity error */
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#define ICU_PCI_POATAI 21 /* PCI outbound ATU target abort */
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#define ICU_PCI_POAMAI 22 /* PCI outbound ATU master abort */
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#define ICU_UARTA 24 /* UART A */
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#define ICU_UARTB 25 /* UART B */
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#define ICU_PCI_INTA 26 /* PCI INTA# */
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#define ICU_PCI_INTB 27 /* PCI INTB# */
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#define ICU_PCI_INTC 28 /* PCI INTC# */
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#define ICU_PCI_INTD 29 /* PCI INTD# */
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#define ICU_PUSHBUTTON 30 /* push button pulse */
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#define ICU_RESERVED_MASK ((1U << 3) | (1U << 4) | (1U << 5) | \
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(1U << 6) | (1U << 12) | (1U << 13) | \
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(1U << 14) | (1U << 15) | (1U << 17) | \
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(1U << 18) | (1U << 23) | (1U << 31))
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#define ICU_VALID_MASK (~ICU_RESERVED_MASK)
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#define BECC_RSSR 0x0500 /* rotary switch status */
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#define RSSR_POS 0x0000000f /* switch position */
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#define RSSR_BE (1U << 6) /* big-endian jumper */
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#endif /* _BECCREG_H_ */
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