167 lines
4.7 KiB
C
167 lines
4.7 KiB
C
/* $NetBSD: intr.h,v 1.10 2001/01/14 02:00:42 thorpej Exp $ */
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/*
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* Copyright (c) 1996, 1997 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* SH3 Version
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*
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* T.Horiuchi Brains Corp. 5/22/98
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*/
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#ifndef _SH3_INTR_H_
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#define _SH3_INTR_H_
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#ifndef _LOCORE
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volatile int cpl, ipending, astpending;
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int imask[NIPL];
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extern void Xspllower __P((void));
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static __inline int splraise __P((int));
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static __inline void spllower __P((int));
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static __inline void softintr __P((int));
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/*
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* Add a mask to cpl, and return the old value of cpl.
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*/
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static __inline int
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splraise(ncpl)
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register int ncpl;
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{
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int ocpl ;
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ocpl = cpl;
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cpl = ocpl | ncpl;
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return (ocpl);
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}
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/*
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* Restore a value to cpl (unmasking interrupts). If any unmasked
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* interrupts are pending, call Xspllower() to process them.
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*/
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static __inline void
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spllower(ncpl)
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register int ncpl;
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{
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cpl = ncpl;
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if (ipending & ~ncpl)
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Xspllower();
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}
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/*
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* Hardware interrupt masks
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*/
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#define splbio() splraise(imask[IPL_BIO])
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#define splnet() splraise(imask[IPL_NET])
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#define spltty() splraise(imask[IPL_TTY])
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#define splaudio() splraise(imask[IPL_AUDIO])
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#define splclock() splraise(imask[IPL_CLOCK])
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#define splstatclock() splclock()
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#define splserial() splraise(imask[IPL_SERIAL])
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/*
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* Software interrupt masks
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*
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* NOTE: splsoftclock() is used by hardclock() to lower the priority from
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* clock to softclock before it calls softclock().
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*/
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#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
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#define splsoftclock() splraise(imask[IPL_SOFTCLOCK])
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#define splsoftnet() splraise(imask[IPL_SOFTNET])
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#define splsoftserial() splraise(imask[IPL_SOFTSERIAL])
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/*
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* Miscellaneous
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*/
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#define splimp() splraise(imask[IPL_IMP])
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#define splvm() splraise(imask[IPL_IMP])
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#define splhigh() splraise(imask[IPL_HIGH])
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#define splsched() splhigh()
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#define spllock() splhigh()
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#define spl0() spllower(0)
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#define splx(x) spllower(x)
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/*
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* Software interrupt registration
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*
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* We hand-code this to ensure that it's atomic.
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*/
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static __inline void
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softintr(mask)
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register int mask;
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{
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extern void enable_interrupt(void); /* XXX */
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extern void disable_interrupt(void);
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disable_interrupt();
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ipending |= (1 << mask);
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enable_interrupt();
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}
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#define setsoftast() (astpending = 1)
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#define setsoftclock() softintr(SIR_CLOCK)
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#define setsoftnet() softintr(SIR_NET)
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#define setsoftserial() softintr(SIR_SERIAL)
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#endif /* !_LOCORE */
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#define INTEVT_SOFT 0xf00 /* This value is stored to INTEVT reg,
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when software interrupt occured */
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#define INTEVT_TMU0 0x400
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#define INTEVT_TMU1 0x420
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#define INTEVT_TMU2 0x440
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#define INTEVT_SCI0_ERI 0x4e0
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#define INTEVT_SCI0_RXI 0x500
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#define INTEVT_SCI0_TXI 0x520
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#define INTEVT_SCI0_TEI 0x540
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#define INTEVT_WDT 0x560
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#define IS_INTEVT_SCI0(x) ((x == INTEVT_SCI0_ERI) || (x == INTEVT_SCI0_RXI) \
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|| (x == INTEVT_SCI0_TXI) || (x == INTEVT_SCI0_TEI))
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#define INTEVT_PRI 0x4a0 /* Periodic interrupt generated by RTC */
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#if defined(SH4)
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#define INTEVT_SCIF 0x700
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#endif
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#endif /* !_SH3_INTR_H_ */
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