d85a75f583
is the historical name for this interrupt level, and the historical name is going to go away in the near future).
154 lines
5.0 KiB
C
154 lines
5.0 KiB
C
/* $NetBSD: intr.h,v 1.10 2001/01/14 02:00:39 thorpej Exp $ */
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/*-
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* Copyright (c) 1996, 1997, 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HP300_INTR_H_
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#define _HP300_INTR_H_
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#include <machine/psl.h>
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#ifdef _HP300_INTR_H_PRIVATE
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#include <sys/queue.h>
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/*
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* The location and size of the autovectored interrupt portion
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* of the vector table.
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*/
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#define ISRLOC 0x18
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#define NISR 8
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struct isr {
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LIST_ENTRY(isr) isr_link;
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int (*isr_func) __P((void *));
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void *isr_arg;
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int isr_ipl;
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int isr_priority;
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};
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#endif /* _HP300_INTR_H_PRIVATE */
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/*
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* Interrupt "levels". These are a more abstract representation
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* of interrupt levels, and do not have the same meaning as m68k
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* CPU interrupt levels. They serve two purposes:
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*
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* - properly order ISRs in the list for that CPU ipl
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* - compute CPU PSL values for the spl*() calls.
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*/
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#define IPL_NONE 0 /* disable only this interrupt */
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#define IPL_BIO 1 /* disable block I/O interrupts */
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#define IPL_NET 2 /* disable network interrupts */
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#define IPL_TTY 3 /* disable terminal interrupts */
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#define IPL_TTYNOBUF 4 /* IPL_TTY + higher ISR priority */
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#define IPL_CLOCK 5 /* disable clock interrupts */
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#define IPL_HIGH 6 /* disable all interrupts */
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/*
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* Convert PSL values to CPU IPLs and vice-versa.
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*/
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#define PSLTOIPL(x) (((x) >> 8) & 0xf)
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#define IPLTOPSL(x) ((((x) & 0xf) << 8) | PSL_S)
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#ifdef _KERNEL
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/* spl0 requires checking for software interrupts */
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/*
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* This array contains the appropriate PSL_S|PSL_IPL? values
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* to raise interrupt priority to the requested level.
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*/
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extern unsigned short hp300_ipls[];
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#define HP300_IPL_SOFT 0
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#define HP300_IPL_BIO 1
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#define HP300_IPL_NET 2
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#define HP300_IPL_TTY 3
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#define HP300_IPL_IMP 4
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#define HP300_IPL_CLOCK 5
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#define HP300_IPL_HIGH 6
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#define HP300_NIPLS 7
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/* These spl calls are _not_ to be used by machine-independent code. */
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#define splhil() splraise1()
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#define splkbd() splhil()
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/* These spl calls are used by machine-independent code. */
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#define spllowersoftclock() spl1()
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#define splsoft() splraise1()
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#define splsoftclock() splsoft()
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#define splsoftnet() splsoft()
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#define splbio() _splraise(hp300_ipls[HP300_IPL_BIO])
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#define splnet() _splraise(hp300_ipls[HP300_IPL_NET])
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#define spltty() _splraise(hp300_ipls[HP300_IPL_TTY])
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#define splimp() _splraise(hp300_ipls[HP300_IPL_IMP])
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#define splvm() _splraise(hp300_ipls[HP300_IPL_IMP])
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#define splclock() spl6()
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#define splstatclock() splclock()
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#define splhigh() spl7()
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#define splsched() spl7()
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#define spllock() spl7()
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/* watch out for side effects */
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#define splx(s) ((s) & PSL_IPL ? _spl((s)) : spl0())
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/*
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* Simulated software interrupt register.
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*/
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extern volatile u_int8_t ssir;
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#define SIR_NET 0x01
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#define SIR_CLOCK 0x02
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#define siron(mask) \
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__asm __volatile ( "orb %1,%0" : "=m" (ssir) : "i" ((mask)))
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#define siroff(mask) \
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__asm __volatile ( "andb %1,%0" : "=m" (ssir) : "ir" (~(mask)));
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#define setsoftnet() siron(SIR_NET)
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#define setsoftclock() siron(SIR_CLOCK)
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/* locore.s */
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int spl0 __P((void));
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/* intr.c */
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void intr_init __P((void));
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void *intr_establish __P((int (*)(void *), void *, int, int));
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void intr_disestablish __P((void *));
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void intr_dispatch __P((int));
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void intr_printlevels __P((void));
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#endif /* _KERNEL */
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#endif /* _HP300_INTR_H_ */
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