75 lines
3.1 KiB
C
75 lines
3.1 KiB
C
/* $NetBSD: pfcreg.h,v 1.6 2002/04/28 17:10:36 uch Exp $ */
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/*-
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH3_PFCREG_H_
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#define _SH3_PFCREG_H_
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#include <sh3/devreg.h>
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/* address definitions for pin function controller (PFC)*/
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#define SH3_PCTR 0xffffff76 /* 16bit */
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#define SH3_PDTR 0xffffff78 /* 8bit */
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#define SH3_SCSPTR 0xffffff7c /* 8bit */
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/* SH7709, SH7709A */
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#define SH7709_PACR 0xa4000100 /* 16bit */
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#define SH7709_PBCR 0xa4000102 /* 16bit */
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#define SH7709_PCCR 0xa4000104 /* 16bit */
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#define SH7709_PDCR 0xa4000106 /* 16bit */
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#define SH7709_PECR 0xa4000108 /* 16bit */
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#define SH7709_PFCR 0xa400010a /* 16bit */
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#define SH7709_PGCR 0xa400010c /* 16bit */
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#define SH7709_PHCR 0xa400010e /* 16bit */
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#define SH7709_PJCR 0xa4000110 /* 16bit */
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#define SH7709_PKCR 0xa4000112 /* 16bit */
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#define SH7709_PLCR 0xa4000114 /* 16bit */
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#define SH7709_SCPCR 0xa4000116 /* 16bit */
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#define SH7709_PADR 0xa4000120 /* 8bit */
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#define SH7709_PBDR 0xa4000122 /* 8bit */
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#define SH7709_PCDR 0xa4000124 /* 8bit */
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#define SH7709_PDDR 0xa4000126 /* 8bit */
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#define SH7709_PEDR 0xa4000128 /* 8bit */
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#define SH7709_PFDR 0xa400012a /* 8bit */
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#define SH7709_PGDR 0xa400012c /* 8bit */
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#define SH7709_PHDR 0xa400012e /* 8bit */
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#define SH7709_PJDR 0xa4000130 /* 8bit */
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#define SH7709_PKDR 0xa4000132 /* 8bit */
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#define SH7709_PLDR 0xa4000134 /* 8bit */
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#define SH7709_SCPDR 0xa4000136 /* 8bit */
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#define SH4_PCTRA 0xff80002c /* 32bit */
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#define SH4_PDTRA 0xff800030 /* 16bit */
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#define SH4_PCTRB 0xff800040 /* 32bit */
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#define SH4_PDTRB 0xff800044 /* 16bit */
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#define SH4_GPIOIC 0xff800048 /* 16bit */
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#define SH4_SCSPTR1 0xffe0001c /* 8bit */
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#define SH4_SCSPTR2 0xffe80020 /* 16bit */
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#endif /* !_SH3_PFCREG_H_ */
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