576 lines
19 KiB
C
576 lines
19 KiB
C
/* $NetBSD: specialreg.h,v 1.28 2003/01/05 22:47:13 sommerfeld Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)specialreg.h 7.1 (Berkeley) 5/9/91
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*/
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/*
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* Bits in 386 special registers:
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*/
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#define CR0_PE 0x00000001 /* Protected mode Enable */
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#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
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#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
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#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
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#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
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#define CR0_PG 0x80000000 /* PaGing enable */
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/*
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* Bits in 486 special registers:
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*/
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#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
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#define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
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#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
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#define CR0_NW 0x20000000 /* Not Write-through */
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#define CR0_CD 0x40000000 /* Cache Disable */
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/*
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* Cyrix 486 DLC special registers, accessible as IO ports.
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*/
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#define CCR0 0xc0 /* configuration control register 0 */
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#define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */
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#define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
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#define CCR0_A20M 0x04 /* enables A20M# input pin */
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#define CCR0_KEN 0x08 /* enables KEN# input pin */
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#define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */
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#define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */
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#define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */
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#define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */
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#define CCR1 0xc1 /* configuration control register 1 */
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#define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */
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/* the remaining 7 bits of this register are reserved */
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/*
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* bits in the pentiums %cr4 register:
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*/
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#define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
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#define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
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#define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */
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#define CR4_DE 0x00000008 /* debugging extension */
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#define CR4_PSE 0x00000010 /* large (4MB) page size enable */
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#define CR4_PAE 0x00000020 /* physical address extension enable */
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#define CR4_MCE 0x00000040 /* machine check enable */
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#define CR4_PGE 0x00000080 /* page global enable */
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#define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
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#define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */
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#define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
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/*
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* CPUID "features" bits:
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*/
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#define CPUID_FPU 0x00000001 /* processor has an FPU? */
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#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
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#define CPUID_DE 0x00000004 /* has debugging extension */
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#define CPUID_PSE 0x00000008 /* has page 4MB page size extension */
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#define CPUID_TSC 0x00000010 /* has time stamp counter */
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#define CPUID_MSR 0x00000020 /* has mode specific registers */
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#define CPUID_PAE 0x00000040 /* has phys address extension */
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#define CPUID_MCE 0x00000080 /* has machine check exception */
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#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
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#define CPUID_APIC 0x00000200 /* has enabled APIC */
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#define CPUID_B10 0x00000400 /* reserved, MTRR */
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#define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */
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#define CPUID_MTRR 0x00001000 /* has memory type range register */
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#define CPUID_PGE 0x00002000 /* has page global extension */
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#define CPUID_MCA 0x00004000 /* has machine check architecture */
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#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
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#define CPUID_PAT 0x00010000 /* Page Attribute Table */
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#define CPUID_PSE36 0x00020000 /* 36-bit PSE */
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#define CPUID_PN 0x00040000 /* processor serial number */
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#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
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#define CPUID_B20 0x00100000 /* reserved */
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#define CPUID_DS 0x00200000 /* Debug Store */
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#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
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#define CPUID_MMX 0x00800000 /* MMX supported */
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#define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */
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#define CPUID_SSE 0x02000000 /* streaming SIMD extensions */
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#define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */
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#define CPUID_SS 0x08000000 /* self-snoop */
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#define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
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#define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
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#define CPUID_IA64 0x40000000 /* IA-64 architecture */
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#define CPUID_SBF 0x80000000 /* signal break on FERR */
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#define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \
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"\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR"
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#define CPUID_MASK1 0x00001fff
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#define CPUID_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN\24CFLUSH" \
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"\25B20\26DS\27ACPI\30MMX"
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#define CPUID_MASK2 0x00ffe000
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#define CPUID_FLAGS3 "\20\31FXSR\32SSE\33SSE2\34SS\35HTT\36TM\37IA64\40SBF"
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#define CPUID_MASK3 0xff000000
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/*
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* AMD/VIA processor specific flags.
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*/
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#define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
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#define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
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#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
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#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
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#define CPUID_EXT_FLAGS2 "\20\16PGE\17MCA\20CMOV\21PAT\22PSE36\23PN" \
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"\24MPC\25B20\26B21\27MMXX\30MMX"
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#define CPUID_EXT_FLAGS3 "\20\31FXSR\32SSE\33B26\34B27\35B28\36B29" \
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"\0373DNOW2\0403DNOW"
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#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15)
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#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15)
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#define CPUID2STEPPING(cpuid) ((cpuid) & 15)
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/*
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* Model-specific registers for the i386 family
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*/
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#define MSR_P5_MC_ADDR 0x000 /* P5 only */
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#define MSR_P5_MC_TYPE 0x001 /* P5 only */
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#define MSR_TSC 0x010
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#define MSR_CESR 0x011 /* P5 only (trap on P6) */
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#define MSR_CTR0 0x012 /* P5 only (trap on P6) */
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#define MSR_CTR1 0x013 /* P5 only (trap on P6) */
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#define MSR_APICBASE 0x01b
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#define MSR_EBL_CR_POWERON 0x02a
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#define MSR_TEST_CTL 0x033
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#define MSR_BIOS_UPDT_TRIG 0x079
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#define MSR_BBL_CR_D0 0x088 /* PII+ only */
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#define MSR_BBL_CR_D1 0x089 /* PII+ only */
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#define MSR_BBL_CR_D2 0x08a /* PII+ only */
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#define MSR_BIOS_SIGN 0x08b
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#define MSR_PERFCTR0 0x0c1
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#define MSR_PERFCTR1 0x0c2
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#define MSR_MTRRcap 0x0fe
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#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
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#define MSR_BBL_CR_DECC 0x118 /* PII+ only */
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#define MSR_BBL_CR_CTL 0x119 /* PII+ only */
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#define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
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#define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
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#define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
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#define MSR_SYSENTER_CS 0x174 /* PII+ only */
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#define MSR_SYSENTER_ESP 0x175 /* PII+ only */
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#define MSR_SYSENTER_EIP 0x176 /* PII+ only */
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#define MSR_MCG_CAP 0x179
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#define MSR_MCG_STATUS 0x17a
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#define MSR_MCG_CTL 0x17b
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#define MSR_EVNTSEL0 0x186
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#define MSR_EVNTSEL1 0x187
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#define MSR_DEBUGCTLMSR 0x1d9
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#define MSR_LASTBRANCHFROMIP 0x1db
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#define MSR_LASTBRANCHTOIP 0x1dc
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#define MSR_LASTINTFROMIP 0x1dd
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#define MSR_LASTINTTOIP 0x1de
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#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
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#define MSR_MTRRphysBase0 0x200
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#define MSR_MTRRphysMask0 0x201
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#define MSR_MTRRphysBase1 0x202
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#define MSR_MTRRphysMask1 0x203
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#define MSR_MTRRphysBase2 0x204
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#define MSR_MTRRphysMask2 0x205
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#define MSR_MTRRphysBase3 0x206
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#define MSR_MTRRphysMask3 0x207
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#define MSR_MTRRphysBase4 0x208
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#define MSR_MTRRphysMask4 0x209
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#define MSR_MTRRphysBase5 0x20a
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#define MSR_MTRRphysMask5 0x20b
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#define MSR_MTRRphysBase6 0x20c
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#define MSR_MTRRphysMask6 0x20d
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#define MSR_MTRRphysBase7 0x20e
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#define MSR_MTRRphysMask7 0x20f
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#define MSR_MTRRfix64K_00000 0x250
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#define MSR_MTRRfix16K_80000 0x258
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#define MSR_MTRRfix16K_A0000 0x259
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#define MSR_MTRRfix4K_C0000 0x268
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#define MSR_MTRRfix4K_C8000 0x269
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#define MSR_MTRRfix4K_D0000 0x26a
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#define MSR_MTRRfix4K_D8000 0x26b
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#define MSR_MTRRfix4K_E0000 0x26c
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#define MSR_MTRRfix4K_E8000 0x26d
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#define MSR_MTRRfix4K_F0000 0x26e
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#define MSR_MTRRfix4K_F8000 0x26f
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#define MSR_MTRRdefType 0x2ff
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#define MSR_MC0_CTL 0x400
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#define MSR_MC0_STATUS 0x401
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#define MSR_MC0_ADDR 0x402
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#define MSR_MC0_MISC 0x403
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#define MSR_MC1_CTL 0x404
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#define MSR_MC1_STATUS 0x405
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#define MSR_MC1_ADDR 0x406
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#define MSR_MC1_MISC 0x407
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#define MSR_MC2_CTL 0x408
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#define MSR_MC2_STATUS 0x409
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#define MSR_MC2_ADDR 0x40a
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#define MSR_MC2_MISC 0x40b
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#define MSR_MC4_CTL 0x40c
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#define MSR_MC4_STATUS 0x40d
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#define MSR_MC4_ADDR 0x40e
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#define MSR_MC4_MISC 0x40f
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#define MSR_MC3_CTL 0x410
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#define MSR_MC3_STATUS 0x411
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#define MSR_MC3_ADDR 0x412
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#define MSR_MC3_MISC 0x413
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/*
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* AMD K6/K7 MSRs.
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*/
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#define MSR_K6_UWCCR 0xc0000085
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#define MSR_K7_EVNTSEL0 0xc0010000
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#define MSR_K7_EVNTSEL1 0xc0010001
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#define MSR_K7_EVNTSEL2 0xc0010002
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#define MSR_K7_EVNTSEL3 0xc0010003
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#define MSR_K7_PERFCTR0 0xc0010004
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#define MSR_K7_PERFCTR1 0xc0010005
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#define MSR_K7_PERFCTR2 0xc0010006
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#define MSR_K7_PERFCTR3 0xc0010007
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/*
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* Constants related to MTRRs
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*/
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#define MTRR_N64K 8 /* numbers of fixed-size entries */
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#define MTRR_N16K 16
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#define MTRR_N4K 64
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/*
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* the following four 3-byte registers control the non-cacheable regions.
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* These registers must be written as three separate bytes.
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*
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* NCRx+0: A31-A24 of starting address
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* NCRx+1: A23-A16 of starting address
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* NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
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*
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* The non-cacheable region's starting address must be aligned to the
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* size indicated by the NCR_SIZE_xx field.
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*/
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#define NCR1 0xc4
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#define NCR2 0xc7
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#define NCR3 0xca
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#define NCR4 0xcd
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#define NCR_SIZE_0K 0
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#define NCR_SIZE_4K 1
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#define NCR_SIZE_8K 2
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#define NCR_SIZE_16K 3
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#define NCR_SIZE_32K 4
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#define NCR_SIZE_64K 5
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#define NCR_SIZE_128K 6
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#define NCR_SIZE_256K 7
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#define NCR_SIZE_512K 8
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#define NCR_SIZE_1M 9
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#define NCR_SIZE_2M 10
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#define NCR_SIZE_4M 11
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#define NCR_SIZE_8M 12
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#define NCR_SIZE_16M 13
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#define NCR_SIZE_32M 14
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#define NCR_SIZE_4G 15
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/*
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* Performance monitor events.
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*
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* Note that 586-class and 686-class CPUs have different performance
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* monitors available, and they are accessed differently:
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*
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* 686-class: `rdpmc' instruction
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* 586-class: `rdmsr' instruction, CESR MSR
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*
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* The descriptions of these events are too lenghy to include here.
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* See Appendix A of "Intel Architecture Software Developer's
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* Manual, Volume 3: System Programming" for more information.
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*/
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/*
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* 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits
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* is CTR1.
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*/
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#define PMC5_CESR_EVENT 0x003f
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#define PMC5_CESR_OS 0x0040
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#define PMC5_CESR_USR 0x0080
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#define PMC5_CESR_E 0x0100
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#define PMC5_CESR_P 0x0200
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#define PMC5_DATA_READ 0x00
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#define PMC5_DATA_WRITE 0x01
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#define PMC5_DATA_TLB_MISS 0x02
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#define PMC5_DATA_READ_MISS 0x03
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#define PMC5_DATA_WRITE_MISS 0x04
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#define PMC5_WRITE_M_E 0x05
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#define PMC5_DATA_LINES_WBACK 0x06
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#define PMC5_DATA_CACHE_SNOOP 0x07
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#define PMC5_DATA_CACHE_SNOOP_HIT 0x08
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#define PMC5_MEM_ACCESS_BOTH_PIPES 0x09
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#define PMC5_BANK_CONFLICTS 0x0a
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#define PMC5_MISALIGNED_DATA 0x0b
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#define PMC5_INST_READ 0x0c
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#define PMC5_INST_TLB_MISS 0x0d
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#define PMC5_INST_CACHE_MISS 0x0e
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#define PMC5_SEGMENT_REG_LOAD 0x0f
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#define PMC5_BRANCHES 0x12
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#define PMC5_BTB_HITS 0x13
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#define PMC5_BRANCH_TAKEN 0x14
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#define PMC5_PIPELINE_FLUSH 0x15
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#define PMC5_INST_EXECUTED 0x16
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#define PMC5_INST_EXECUTED_V_PIPE 0x17
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#define PMC5_BUS_UTILIZATION 0x18
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#define PMC5_WRITE_BACKUP_STALL 0x19
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#define PMC5_DATA_READ_STALL 0x1a
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#define PMC5_WRITE_E_M_STALL 0x1b
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#define PMC5_LOCKED_BUS 0x1c
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#define PMC5_IO_CYCLE 0x1d
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#define PMC5_NONCACHE_MEM_READ 0x1e
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#define PMC5_AGI_STALL 0x1f
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#define PMC5_FLOPS 0x22
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#define PMC5_BP0_MATCH 0x23
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#define PMC5_BP1_MATCH 0x24
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#define PMC5_BP2_MATCH 0x25
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#define PMC5_BP3_MATCH 0x26
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#define PMC5_HARDWARE_INTR 0x27
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#define PMC5_DATA_RW 0x28
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#define PMC5_DATA_RW_MISS 0x29
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/*
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* 686-class Event Selector MSR format.
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*/
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#define PMC6_EVTSEL_EVENT 0x000000ff
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#define PMC6_EVTSEL_UNIT 0x0000ff00
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#define PMC6_EVTSEL_UNIT_SHIFT 8
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#define PMC6_EVTSEL_USR (1 << 16)
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#define PMC6_EVTSEL_OS (1 << 17)
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#define PMC6_EVTSEL_E (1 << 18)
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#define PMC6_EVTSEL_PC (1 << 19)
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#define PMC6_EVTSEL_INT (1 << 20)
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#define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */
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#define PMC6_EVTSEL_INV (1 << 23)
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#define PMC6_EVTSEL_COUNTER_MASK 0xff000000
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#define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24
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/* Data Cache Unit */
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#define PMC6_DATA_MEM_REFS 0x43
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#define PMC6_DCU_LINES_IN 0x45
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#define PMC6_DCU_M_LINES_IN 0x46
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#define PMC6_DCU_M_LINES_OUT 0x47
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#define PMC6_DCU_MISS_OUTSTANDING 0x48
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/* Instruction Fetch Unit */
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#define PMC6_IFU_IFETCH 0x80
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#define PMC6_IFU_IFETCH_MISS 0x81
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#define PMC6_ITLB_MISS 0x85
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#define PMC6_IFU_MEM_STALL 0x86
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#define PMC6_ILD_STALL 0x87
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/* L2 Cache */
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#define PMC6_L2_IFETCH 0x28
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#define PMC6_L2_LD 0x29
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#define PMC6_L2_ST 0x2a
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#define PMC6_L2_LINES_IN 0x24
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#define PMC6_L2_LINES_OUT 0x26
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#define PMC6_L2_M_LINES_INM 0x25
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#define PMC6_L2_M_LINES_OUTM 0x27
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#define PMC6_L2_RQSTS 0x2e
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#define PMC6_L2_ADS 0x21
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#define PMC6_L2_DBUS_BUSY 0x22
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#define PMC6_L2_DBUS_BUSY_RD 0x23
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/* External Bus Logic */
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#define PMC6_BUS_DRDY_CLOCKS 0x62
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#define PMC6_BUS_LOCK_CLOCKS 0x63
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#define PMC6_BUS_REQ_OUTSTANDING 0x60
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#define PMC6_BUS_TRAN_BRD 0x65
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#define PMC6_BUS_TRAN_RFO 0x66
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#define PMC6_BUS_TRANS_WB 0x67
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#define PMC6_BUS_TRAN_IFETCH 0x68
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#define PMC6_BUS_TRAN_INVAL 0x69
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#define PMC6_BUS_TRAN_PWR 0x6a
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#define PMC6_BUS_TRANS_P 0x6b
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#define PMC6_BUS_TRANS_IO 0x6c
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#define PMC6_BUS_TRAN_DEF 0x6d
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#define PMC6_BUS_TRAN_BURST 0x6e
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#define PMC6_BUS_TRAN_ANY 0x70
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#define PMC6_BUS_TRAN_MEM 0x6f
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#define PMC6_BUS_DATA_RCV 0x64
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#define PMC6_BUS_BNR_DRV 0x61
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#define PMC6_BUS_HIT_DRV 0x7a
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#define PMC6_BUS_HITM_DRDV 0x7b
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#define PMC6_BUS_SNOOP_STALL 0x7e
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/* Floating Point Unit */
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#define PMC6_FLOPS 0xc1
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#define PMC6_FP_COMP_OPS_EXE 0x10
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#define PMC6_FP_ASSIST 0x11
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#define PMC6_MUL 0x12
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#define PMC6_DIV 0x12
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#define PMC6_CYCLES_DIV_BUSY 0x14
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/* Memory Ordering */
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#define PMC6_LD_BLOCKS 0x03
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#define PMC6_SB_DRAINS 0x04
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#define PMC6_MISALIGN_MEM_REF 0x05
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#define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */
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#define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */
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/* Instruction Decoding and Retirement */
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#define PMC6_INST_RETIRED 0xc0
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#define PMC6_UOPS_RETIRED 0xc2
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#define PMC6_INST_DECODED 0xd0
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#define PMC6_EMON_KNI_INST_RETIRED 0xd8
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#define PMC6_EMON_KNI_COMP_INST_RET 0xd9
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/* Interrupts */
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#define PMC6_HW_INT_RX 0xc8
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#define PMC6_CYCLES_INT_MASKED 0xc6
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#define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
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/* Branches */
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#define PMC6_BR_INST_RETIRED 0xc4
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#define PMC6_BR_MISS_PRED_RETIRED 0xc5
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#define PMC6_BR_TAKEN_RETIRED 0xc9
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#define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
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#define PMC6_BR_INST_DECODED 0xe0
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#define PMC6_BTB_MISSES 0xe2
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#define PMC6_BR_BOGUS 0xe4
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#define PMC6_BACLEARS 0xe6
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/* Stalls */
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#define PMC6_RESOURCE_STALLS 0xa2
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#define PMC6_PARTIAL_RAT_STALLS 0xd2
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/* Segment Register Loads */
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#define PMC6_SEGMENT_REG_LOADS 0x06
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/* Clocks */
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#define PMC6_CPU_CLK_UNHALTED 0x79
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/* MMX Unit */
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#define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */
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#define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */
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#define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */
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#define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */
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#define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */
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#define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */
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#define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */
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/* Segment Register Renaming */
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#define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */
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#define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */
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#define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
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/*
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* AMD K7 Event Selector MSR format.
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*/
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#define K7_EVTSEL_EVENT 0x000000ff
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#define K7_EVTSEL_UNIT 0x0000ff00
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#define K7_EVTSEL_UNIT_SHIFT 8
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#define K7_EVTSEL_USR (1 << 16)
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#define K7_EVTSEL_OS (1 << 17)
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#define K7_EVTSEL_E (1 << 18)
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#define K7_EVTSEL_PC (1 << 19)
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#define K7_EVTSEL_INT (1 << 20)
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#define K7_EVTSEL_EN (1 << 22)
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#define K7_EVTSEL_INV (1 << 23)
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#define K7_EVTSEL_COUNTER_MASK 0xff000000
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#define K7_EVTSEL_COUNTER_MASK_SHIFT 24
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|
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/* Segment Register Loads */
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#define K7_SEGMENT_REG_LOADS 0x20
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#define K7_STORES_TO_ACTIVE_INST_STREAM 0x21
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/* Data Cache Unit */
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#define K7_DATA_CACHE_ACCESS 0x40
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#define K7_DATA_CACHE_MISS 0x41
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#define K7_DATA_CACHE_REFILL 0x42
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#define K7_DATA_CACHE_REFILL_SYSTEM 0x43
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#define K7_DATA_CACHE_WBACK 0x44
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#define K7_L2_DTLB_HIT 0x45
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#define K7_L2_DTLB_MISS 0x46
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#define K7_MISALIGNED_DATA_REF 0x47
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#define K7_SYSTEM_REQUEST 0x64
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#define K7_SYSTEM_REQUEST_TYPE 0x65
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#define K7_SNOOP_HIT 0x73
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#define K7_SINGLE_BIT_ECC_ERROR 0x74
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#define K7_CACHE_LINE_INVAL 0x75
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|
#define K7_CYCLES_PROCESSOR_IS_RUNNING 0x76
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|
#define K7_L2_REQUEST 0x79
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|
#define K7_L2_REQUEST_BUSY 0x7a
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|
|
|
/* Instruction Fetch Unit */
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|
#define K7_IFU_IFETCH 0x80
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|
#define K7_IFU_IFETCH_MISS 0x81
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|
#define K7_IFU_REFILL_FROM_L2 0x82
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#define K7_IFU_REFILL_FROM_SYSTEM 0x83
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#define K7_ITLB_L1_MISS 0x84
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#define K7_ITLB_L2_MISS 0x85
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#define K7_SNOOP_RESYNC 0x86
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#define K7_IFU_STALL 0x87
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|
|
|
#define K7_RETURN_STACK_HITS 0x88
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|
#define K7_RETURN_STACK_OVERFLOW 0x89
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|
|
|
/* Retired */
|
|
#define K7_RETIRED_INST 0xc0
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|
#define K7_RETIRED_OPS 0xc1
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|
#define K7_RETIRED_BRANCHES 0xc2
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|
#define K7_RETIRED_BRANCH_MISPREDICTED 0xc3
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|
#define K7_RETIRED_TAKEN_BRANCH 0xc4
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|
#define K7_RETIRED_TAKEN_BRANCH_MISPREDICTED 0xc5
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|
#define K7_RETIRED_FAR_CONTROL_TRANSFER 0xc6
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|
#define K7_RETIRED_RESYNC_BRANCH 0xc7
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|
#define K7_RETIRED_NEAR_RETURNS 0xc8
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|
#define K7_RETIRED_NEAR_RETURNS_MISPREDICTED 0xc9
|
|
#define K7_RETIRED_INDIRECT_MISPREDICTED 0xca
|
|
|
|
/* Interrupts */
|
|
#define K7_CYCLES_INT_MASKED 0xcd
|
|
#define K7_CYCLES_INT_PENDING_AND_MASKED 0xce
|
|
#define K7_HW_INTR_RECV 0xcf
|
|
|
|
#define K7_INSTRUCTION_DECODER_EMPTY 0xd0
|
|
#define K7_DISPATCH_STALLS 0xd1
|
|
#define K7_BRANCH_ABORTS_TO_RETIRE 0xd2
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|
#define K7_SERIALIZE 0xd3
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|
#define K7_SEGMENT_LOAD_STALL 0xd4
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|
#define K7_ICU_FULL 0xd5
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|
#define K7_RESERVATION_STATIONS_FULL 0xd6
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|
#define K7_FPU_FULL 0xd7
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|
#define K7_LS_FULL 0xd8
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|
#define K7_ALL_QUIET_STALL 0xd9
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|
#define K7_FAR_TRANSFER_OR_RESYNC_BRANCH_PENDING 0xda
|
|
|
|
#define K7_BP0_MATCH 0xdc
|
|
#define K7_BP1_MATCH 0xdd
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|
#define K7_BP2_MATCH 0xde
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|
#define K7_BP3_MATCH 0xdf
|