53e8f6c919
Remarks:
1. All processors (x86 or not) for which the vendor has implemented
ACPI I/O access routines are supported. Native instructions are
currently supported only for Intel's "Enhanced Speedstep". Code for
"PowerNow!" (AMD) will be merged later. Native support for VIA's
"PowerSaver" will be investigated.
2. Backwards compatibility with existing userland code is maintained.
Comparable to the case with cpu_idle(9), the ACPI CPU driver
installs alternative functions for the existing sysctl(8) controls.
The "native" behavior (if any) is restored upon detachment.
3. The dynamic nature of ACPI-provided P-states needs more investigation.
The maximum frequency induced (but not forced) by the firmware may
change dynamically. Currently, the sysctl(8) controls error out with
a value larger than the dynamic maximum. The code itself does not
however yet react to the notifications from the firmware by changing
the frequencies in-place. Presumably the system administrator should
be able to choose whether to use dynamic or static frequencies.
203 lines
6.7 KiB
C
203 lines
6.7 KiB
C
/* $NetBSD: acpi_cpu.h,v 1.9 2010/08/08 16:58:42 jruoho Exp $ */
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/*-
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* Copyright (c) 2010 Jukka Ruohonen <jruohonen@iki.fi>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _SYS_DEV_ACPI_ACPI_CPU_H
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#define _SYS_DEV_ACPI_ACPI_CPU_H
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/*
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* The following _PDC values are based on:
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*
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* Intel Corporation: Intel Processor-Specific ACPI
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* Interface Specification, September 2006, Revision 005.
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*
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* http://download.intel.com/technology/IAPC/acpi/downloads/30222305.pdf
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*
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* For other relevant reading, see for instance:
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*
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* Advanced Micro Devices: Using ACPI to Report APML P-State
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* Limit Changes to Operating Systems and VMM's. August 7, 2009.
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*
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* http://developer.amd.com/Assets/ACPI-APML-PState-rev12.pdf
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*/
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#define ACPICPU_PDC_REVID 0x1
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#define ACPICPU_PDC_SMP 0xA
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#define ACPICPU_PDC_MSR 0x1
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#define ACPICPU_PDC_P_FFH __BIT(0) /* SpeedStep MSRs */
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#define ACPICPU_PDC_C_C1_HALT __BIT(1) /* C1 "I/O then halt" */
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#define ACPICPU_PDC_T_FFH __BIT(2) /* OnDemand throttling MSRs */
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#define ACPICPU_PDC_C_C1PT __BIT(3) /* SMP C1, Px, and Tx (same) */
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#define ACPICPU_PDC_C_C2C3 __BIT(4) /* SMP C2 and C3 (same) */
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#define ACPICPU_PDC_P_SW __BIT(5) /* SMP Px (different) */
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#define ACPICPU_PDC_C_SW __BIT(6) /* SMP Cx (different) */
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#define ACPICPU_PDC_T_SW __BIT(7) /* SMP Tx (different) */
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#define ACPICPU_PDC_C_C1_FFH __BIT(8) /* SMP C1 native beyond halt */
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#define ACPICPU_PDC_C_C2C3_FFH __BIT(9) /* SMP C2 and C2 native */
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#define ACPICPU_PDC_P_HW __BIT(11) /* Px hardware coordination */
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#define ACPICPU_PDC_GAS_HW __BIT(0) /* HW-coordinated state */
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#define ACPICPU_PDC_GAS_BM __BIT(1) /* Bus master check required */
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/*
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* Notify values.
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*/
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#define ACPICPU_P_NOTIFY 0x80 /* _PPC */
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#define ACPICPU_C_NOTIFY 0x81 /* _CST */
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#define ACPICPU_T_NOTIFY 0x82 /* _TPC */
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/*
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* C-states.
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*/
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#define ACPICPU_C_C2_LATENCY_MAX 100 /* us */
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#define ACPICPU_C_C3_LATENCY_MAX 1000 /* us */
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#define ACPICPU_C_STATE_HALT 0x01
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#define ACPICPU_C_STATE_FFH 0x02
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#define ACPICPU_C_STATE_SYSIO 0x03
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/*
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* P-states.
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*/
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#define ACPICPU_P_STATE_RETRY 100
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#define ACPICPU_P_STATE_UNKNOWN 0x0
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/*
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* Flags.
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*/
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#define ACPICPU_FLAG_C __BIT(0) /* C-states supported */
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#define ACPICPU_FLAG_P __BIT(1) /* P-states supported */
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#define ACPICPU_FLAG_T __BIT(2) /* T-states supported */
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#define ACPICPU_FLAG_C_CST __BIT(3) /* C-states with _CST */
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#define ACPICPU_FLAG_C_FADT __BIT(4) /* C-states with FADT */
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#define ACPICPU_FLAG_C_BM __BIT(5) /* Bus master control */
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#define ACPICPU_FLAG_C_BM_STS __BIT(6) /* Bus master check required */
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#define ACPICPU_FLAG_C_ARB __BIT(7) /* Bus master arbitration */
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#define ACPICPU_FLAG_C_NOC3 __BIT(8) /* C3 disabled (quirk) */
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#define ACPICPU_FLAG_C_FFH __BIT(9) /* MONITOR/MWAIT supported */
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#define ACPICPU_FLAG_C_C1E __BIT(10) /* AMD C1E detected */
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#define ACPICPU_FLAG_P_PPC __BIT(11) /* Dynamic freq. with _PPC */
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#define ACPICPU_FLAG_P_FFH __BIT(12) /* EST etc. supported */
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/*
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* This is AML_RESOURCE_GENERIC_REGISTER,
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* included here separately for convenience.
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*/
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struct acpicpu_reg {
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uint8_t reg_desc;
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uint16_t reg_reslen;
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uint8_t reg_spaceid;
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uint8_t reg_bitwidth;
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uint8_t reg_bitoffset;
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uint8_t reg_accesssize;
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uint64_t reg_addr;
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} __packed;
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struct acpicpu_cstate {
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uint64_t cs_stat;
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uint64_t cs_addr;
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uint32_t cs_power; /* mW */
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uint32_t cs_latency; /* us */
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int cs_method;
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int cs_flags;
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};
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struct acpicpu_pstate {
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uint64_t ps_stat;
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uint32_t ps_freq; /* MHz */
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uint32_t ps_power; /* mW */
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uint32_t ps_latency; /* us */
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uint32_t ps_latency_bm; /* us */
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uint32_t ps_control;
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uint32_t ps_status;
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};
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struct acpicpu_object {
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uint32_t ao_procid;
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uint32_t ao_pblklen;
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uint32_t ao_pblkaddr;
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};
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struct acpicpu_softc {
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device_t sc_dev;
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struct acpi_devnode *sc_node;
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struct acpicpu_object sc_object;
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struct acpicpu_cstate sc_cstate[ACPI_C_STATE_COUNT];
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uint32_t sc_cstate_sleep;
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struct acpicpu_pstate *sc_pstate;
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struct acpicpu_reg sc_pstate_control;
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struct acpicpu_reg sc_pstate_status;
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uint32_t sc_pstate_current;
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uint32_t sc_pstate_count;
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uint32_t sc_pstate_max;
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kmutex_t sc_mtx;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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uint32_t sc_cap;
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uint32_t sc_flags;
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cpuid_t sc_cpuid;
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bool sc_cold;
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};
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void acpicpu_cstate_attach(device_t);
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int acpicpu_cstate_detach(device_t);
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int acpicpu_cstate_start(device_t);
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bool acpicpu_cstate_suspend(device_t);
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bool acpicpu_cstate_resume(device_t);
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void acpicpu_cstate_callback(void *);
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void acpicpu_cstate_idle(void);
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void acpicpu_pstate_attach(device_t);
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int acpicpu_pstate_detach(device_t);
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int acpicpu_pstate_start(device_t);
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bool acpicpu_pstate_suspend(device_t);
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bool acpicpu_pstate_resume(device_t);
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void acpicpu_pstate_callback(void *);
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int acpicpu_pstate_get(struct acpicpu_softc *, uint32_t *);
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int acpicpu_pstate_set(struct acpicpu_softc *, uint32_t);
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uint32_t acpicpu_md_cap(void);
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uint32_t acpicpu_md_quirks(void);
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uint32_t acpicpu_md_cpus_running(void);
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int acpicpu_md_idle_init(void);
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int acpicpu_md_idle_start(void);
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int acpicpu_md_idle_stop(void);
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void acpicpu_md_idle_enter(int, int);
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int acpicpu_md_pstate_start(void);
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int acpicpu_md_pstate_stop(void);
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int acpicpu_md_pstate_get(struct acpicpu_softc *, uint32_t *);
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int acpicpu_md_pstate_set(struct acpicpu_pstate *);
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#endif /* !_SYS_DEV_ACPI_ACPI_CPU_H */
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