679 lines
17 KiB
C
679 lines
17 KiB
C
/* $NetBSD: cg4.c,v 1.19 1998/06/09 16:10:25 gwr Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)cgthree.c 8.2 (Berkeley) 10/30/93
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*/
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/*
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* color display (cg4) driver.
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*
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* Credits, history:
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* Gordon Ross created this driver based on the cg3 driver from
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* the sparc port as distributed in BSD 4.4 Lite, but included
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* support for only the "type B" adapter (Brooktree DACs).
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* Ezra Story added support for the "type A" (AMD DACs).
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*
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* Todo:
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* Make this driver handle video interrupts.
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* Defer colormap updates to vertical retrace interrupts.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/device.h>
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#include <sys/ioctl.h>
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#include <sys/malloc.h>
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#include <sys/mman.h>
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#include <sys/proc.h>
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#include <sys/tty.h>
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#include <vm/vm.h>
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <machine/fbio.h>
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#include <machine/idprom.h>
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#include <machine/pmap.h>
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#include <sun3/dev/fbvar.h>
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#include <sun3/dev/btreg.h>
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#include <sun3/dev/cg4reg.h>
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#include <sun3/dev/p4reg.h>
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union bt_cmap_u {
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u_char btcm_char[256 * 3]; /* raw data */
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u_char btcm_rgb[256][3]; /* 256 R/G/B entries */
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u_int btcm_int[256 * 3 / 4]; /* the way the chip gets loaded */
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};
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#define CG4_TYPE_A 0 /* AMD DACs */
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#define CG4_TYPE_B 1 /* Brooktree DACs */
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cdev_decl(cg4);
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#define CG4_MMAP_SIZE (CG4_OVERLAY_SIZE + CG4_ENABLE_SIZE + CG4_PIXMAP_SIZE)
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#define CMAP_SIZE 256
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struct soft_cmap {
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u_char r[CMAP_SIZE];
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u_char g[CMAP_SIZE];
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u_char b[CMAP_SIZE];
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};
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/* per-display variables */
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struct cg4_softc {
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struct device sc_dev; /* base device */
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struct fbdevice sc_fb; /* frame buffer device */
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int sc_cg4type; /* A or B */
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int sc_pa_overlay; /* phys. addr. of overlay plane */
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int sc_pa_enable; /* phys. addr. of enable plane */
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int sc_pa_pixmap; /* phys. addr. of color plane */
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int sc_video_on; /* zero if blanked */
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void *sc_va_cmap; /* Colormap h/w (mapped KVA) */
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void *sc_btcm; /* Soft cmap, Brooktree format */
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void (*sc_ldcmap) __P((struct cg4_softc *));
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struct soft_cmap sc_cmap; /* Soft cmap, user format */
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};
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/* autoconfiguration driver */
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static void cg4attach __P((struct device *, struct device *, void *));
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static int cg4match __P((struct device *, struct cfdata *, void *));
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struct cfattach cgfour_ca = {
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sizeof(struct cg4_softc), cg4match, cg4attach
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};
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extern struct cfdriver cgfour_cd;
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static int cg4gattr __P((struct fbdevice *, void *));
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static int cg4gvideo __P((struct fbdevice *, void *));
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static int cg4svideo __P((struct fbdevice *, void *));
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static int cg4getcmap __P((struct fbdevice *, void *));
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static int cg4putcmap __P((struct fbdevice *, void *));
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#ifdef _SUN3_
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static void cg4a_init __P((struct cg4_softc *));
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static void cg4a_ldcmap __P((struct cg4_softc *));
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#endif /* SUN3 */
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static void cg4b_init __P((struct cg4_softc *));
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static void cg4b_ldcmap __P((struct cg4_softc *));
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static struct fbdriver cg4_fbdriver = {
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cg4open, cg4close, cg4mmap, cg4gattr,
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cg4gvideo, cg4svideo,
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cg4getcmap, cg4putcmap };
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/*
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* Match a cg4.
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*/
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static int
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cg4match(parent, cf, args)
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struct device *parent;
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struct cfdata *cf;
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void *args;
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{
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struct confargs *ca = args;
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int mid, p4id, peekval, tmp;
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void *p4reg;
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/* No default address support. */
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if (ca->ca_paddr == -1)
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return (0);
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/*
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* Slight hack here: The low four bits of the
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* config flags, if set, restrict the match to
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* that machine "implementation" only.
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*/
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mid = cf->cf_flags & IDM_IMPL_MASK;
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if (mid && (mid != (cpu_machine_id & IDM_IMPL_MASK)))
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return (0);
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/*
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* The config flag 0x10 if set means we are
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* looking for a Type A board (3/110).
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*/
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if (cf->cf_flags & 0x10) {
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#ifdef _SUN3_
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/* Type A: Check for AMD RAMDACs in control space. */
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if (bus_peek(BUS_OBIO, CG4A_OBIO_CMAP, 1) == -1)
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return (0);
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/* Check for the overlay plane. */
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tmp = ca->ca_paddr + CG4A_OFF_OVERLAY;
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if (bus_peek(ca->ca_bustype, tmp, 1) == -1)
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return (0);
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/* OK, it looks like a Type A. */
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return (1);
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#else /* SUN3 */
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/* Only the Sun3/110 ever has a type A. */
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return (0);
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#endif /* SUN3 */
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}
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/*
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* From here on, it is a type B or nothing.
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* The config flag 0x20 if set means there
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* is no P4 register. (bus error)
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*/
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if ((cf->cf_flags & 0x20) == 0) {
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p4reg = bus_tmapin(ca->ca_bustype, ca->ca_paddr);
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peekval = peek_long(p4reg);
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p4id = (peekval == -1) ?
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P4_NOTFOUND : fb_pfour_id(p4reg);
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bus_tmapout(p4reg);
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if (peekval == -1)
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return (0);
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if (p4id != P4_ID_COLOR8P1) {
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#ifdef DEBUG
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printf("cgfour at 0x%x match p4id=0x%x fails\n",
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ca->ca_paddr, p4id & 0xFF);
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#endif
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return (0);
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}
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}
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/*
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* Check for CMAP hardware and overlay plane.
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*/
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tmp = ca->ca_paddr + CG4B_OFF_CMAP;
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if (bus_peek(ca->ca_bustype, tmp, 4) == -1)
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return (0);
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tmp = ca->ca_paddr + CG4B_OFF_OVERLAY;
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if (bus_peek(ca->ca_bustype, tmp, 1) == -1)
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return (0);
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return (1);
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}
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/*
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* Attach a display. We need to notice if it is the console, too.
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*/
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static void
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cg4attach(parent, self, args)
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struct device *parent, *self;
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void *args;
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{
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struct cg4_softc *sc = (struct cg4_softc *)self;
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struct fbdevice *fb = &sc->sc_fb;
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struct confargs *ca = args;
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struct fbtype *fbt;
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int tmp;
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fbt = &fb->fb_fbtype;
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fbt->fb_type = FBTYPE_SUN4COLOR;
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fbt->fb_width = 1152; /* default - see below */
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fbt->fb_height = 900; /* default - see below */
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fbt->fb_depth = 8;
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fbt->fb_cmsize = 256;
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fbt->fb_size = CG4_MMAP_SIZE;
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fb->fb_driver = &cg4_fbdriver;
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fb->fb_private = sc;
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fb->fb_name = sc->sc_dev.dv_xname;
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fb->fb_flags = sc->sc_dev.dv_cfdata->cf_flags;
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/*
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* The config flag 0x10 if set means we are
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* attaching a Type A (3/110) which has the
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* AMD RAMDACs in control space, and no P4.
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*/
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if (fb->fb_flags & 0x10) {
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#ifdef _SUN3_
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sc->sc_cg4type = CG4_TYPE_A;
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sc->sc_ldcmap = cg4a_ldcmap;
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sc->sc_pa_overlay = ca->ca_paddr + CG4A_OFF_OVERLAY;
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sc->sc_pa_enable = ca->ca_paddr + CG4A_OFF_ENABLE;
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sc->sc_pa_pixmap = ca->ca_paddr + CG4A_OFF_PIXMAP;
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sc->sc_va_cmap = bus_mapin(BUS_OBIO, CG4A_OBIO_CMAP,
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sizeof(struct amd_regs));
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cg4a_init(sc);
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#else /* SUN3 */
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panic("cgfour flags 0x10");
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#endif /* SUN3 */
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} else {
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sc->sc_cg4type = CG4_TYPE_B;
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sc->sc_ldcmap = cg4b_ldcmap;
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sc->sc_pa_overlay = ca->ca_paddr + CG4B_OFF_OVERLAY;
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sc->sc_pa_enable = ca->ca_paddr + CG4B_OFF_ENABLE;
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sc->sc_pa_pixmap = ca->ca_paddr + CG4B_OFF_PIXMAP;
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tmp = ca->ca_paddr + CG4B_OFF_CMAP;
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sc->sc_va_cmap = bus_mapin(ca->ca_bustype, tmp,
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sizeof(struct bt_regs));
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cg4b_init(sc);
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}
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if ((fb->fb_flags & 0x20) == 0) {
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/* It is supposed to have a P4 register. */
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fb->fb_pfour = bus_mapin(ca->ca_bustype, ca->ca_paddr, 4);
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}
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/*
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* Determine width and height as follows:
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* If it has a P4 register, use that;
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* else if unit==0, use the EEPROM size,
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* else make our best guess.
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*/
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if (fb->fb_pfour)
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fb_pfour_setsize(fb);
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else if (sc->sc_dev.dv_unit == 0)
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fb_eeprom_setsize(fb);
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else {
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/* Guess based on machine ID. */
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switch (cpu_machine_id) {
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default:
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/* Leave the defaults set above. */
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break;
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}
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}
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printf(" (%dx%d)\n", fbt->fb_width, fbt->fb_height);
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/*
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* Make sure video is on. This driver uses a
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* black colormap to blank the screen, so if
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* there is any global enable, set it here.
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*/
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tmp = 1;
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cg4svideo(fb, &tmp);
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if (fb->fb_pfour)
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fb_pfour_set_video(fb, 1);
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else
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enable_video(1);
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/* Let /dev/fb know we are here. */
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fb_attach(fb, 4);
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}
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int
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cg4open(dev, flags, mode, p)
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dev_t dev;
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int flags, mode;
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struct proc *p;
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{
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int unit = minor(dev);
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if (unit >= cgfour_cd.cd_ndevs || cgfour_cd.cd_devs[unit] == NULL)
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return (ENXIO);
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return (0);
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}
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int
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cg4close(dev, flags, mode, p)
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dev_t dev;
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int flags, mode;
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struct proc *p;
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{
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return (0);
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}
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int
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cg4ioctl(dev, cmd, data, flags, p)
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dev_t dev;
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u_long cmd;
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caddr_t data;
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int flags;
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struct proc *p;
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{
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struct cg4_softc *sc = cgfour_cd.cd_devs[minor(dev)];
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return (fbioctlfb(&sc->sc_fb, cmd, data));
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}
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/*
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* Return the address that would map the given device at the given
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* offset, allowing for the given protection, or return -1 for error.
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*
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* X11 expects its mmap'd region to look like this:
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* 128k overlay data memory
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* 128k overlay enable bitmap
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* 1024k color memory
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*
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* The hardware looks completely different.
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*/
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int
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cg4mmap(dev, off, prot)
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dev_t dev;
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int off;
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int prot;
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{
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struct cg4_softc *sc = cgfour_cd.cd_devs[minor(dev)];
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register int physbase;
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if (off & PGOFSET)
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panic("cg4mmap");
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if ((off < 0) || (off >= CG4_MMAP_SIZE))
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return (-1);
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if (off < 0x40000) {
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if (off < 0x20000) {
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physbase = sc->sc_pa_overlay;
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} else {
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/* enable plane */
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off -= 0x20000;
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physbase = sc->sc_pa_enable;
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}
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} else {
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/* pixel map */
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off -= 0x40000;
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physbase = sc->sc_pa_pixmap;
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}
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/*
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* I turned on PMAP_NC here to disable the cache as I was
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* getting horribly broken behaviour without it.
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*/
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return ((physbase + off) | PMAP_NC);
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}
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/*
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* Internal ioctl functions.
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*/
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/* FBIOGATTR: */
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static int cg4gattr(fb, data)
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struct fbdevice *fb;
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void *data;
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{
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struct fbgattr *fba = data;
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fba->real_type = fb->fb_fbtype.fb_type;
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fba->owner = 0; /* XXX - TIOCCONS stuff? */
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fba->fbtype = fb->fb_fbtype;
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fba->sattr.flags = 0;
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fba->sattr.emu_type = fb->fb_fbtype.fb_type;
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fba->sattr.dev_specific[0] = -1;
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fba->emu_types[0] = fb->fb_fbtype.fb_type;
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fba->emu_types[1] = -1;
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return (0);
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}
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/* FBIOGVIDEO: */
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static int cg4gvideo(fb, data)
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struct fbdevice *fb;
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void *data;
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{
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struct cg4_softc *sc = fb->fb_private;
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int *on = data;
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*on = sc->sc_video_on;
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return (0);
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}
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/* FBIOSVIDEO: */
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static int cg4svideo(fb, data)
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struct fbdevice *fb;
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void *data;
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{
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struct cg4_softc *sc = fb->fb_private;
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int *on = data;
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if (sc->sc_video_on == *on)
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return (0);
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sc->sc_video_on = *on;
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(*sc->sc_ldcmap)(sc);
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return (0);
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}
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/*
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* FBIOGETCMAP:
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* Copy current colormap out to user space.
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*/
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static int cg4getcmap(fb, data)
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struct fbdevice *fb;
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void *data;
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{
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struct cg4_softc *sc = fb->fb_private;
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struct soft_cmap *cm = &sc->sc_cmap;
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struct fbcmap *fbcm = data;
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int error, start, count;
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start = fbcm->index;
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count = fbcm->count;
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if ((start < 0) || (start >= CMAP_SIZE) ||
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(count < 0) || (start + count > CMAP_SIZE) )
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return (EINVAL);
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if ((error = copyout(&cm->r[start], fbcm->red, count)) != 0)
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return (error);
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if ((error = copyout(&cm->g[start], fbcm->green, count)) != 0)
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return (error);
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if ((error = copyout(&cm->b[start], fbcm->blue, count)) != 0)
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return (error);
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return (0);
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}
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/*
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* FBIOPUTCMAP:
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* Copy new colormap from user space and load.
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*/
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static int cg4putcmap(fb, data)
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struct fbdevice *fb;
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void *data;
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{
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struct cg4_softc *sc = fb->fb_private;
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struct soft_cmap *cm = &sc->sc_cmap;
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struct fbcmap *fbcm = data;
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int error, start, count;
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start = fbcm->index;
|
|
count = fbcm->count;
|
|
if ((start < 0) || (start >= CMAP_SIZE) ||
|
|
(count < 0) || (start + count > CMAP_SIZE) )
|
|
return (EINVAL);
|
|
|
|
if ((error = copyin(fbcm->red, &cm->r[start], count)) != 0)
|
|
return (error);
|
|
|
|
if ((error = copyin(fbcm->green, &cm->g[start], count)) != 0)
|
|
return (error);
|
|
|
|
if ((error = copyin(fbcm->blue, &cm->b[start], count)) != 0)
|
|
return (error);
|
|
|
|
(*sc->sc_ldcmap)(sc);
|
|
return (0);
|
|
}
|
|
|
|
/****************************************************************
|
|
* Routines for the "Type A" hardware
|
|
****************************************************************/
|
|
#ifdef _SUN3_
|
|
|
|
static void
|
|
cg4a_init(sc)
|
|
struct cg4_softc *sc;
|
|
{
|
|
volatile struct amd_regs *ar = sc->sc_va_cmap;
|
|
struct soft_cmap *cm = &sc->sc_cmap;
|
|
int i;
|
|
|
|
/* Grab initial (current) color map. */
|
|
for(i = 0; i < 256; i++) {
|
|
cm->r[i] = ar->r[i];
|
|
cm->g[i] = ar->g[i];
|
|
cm->b[i] = ar->b[i];
|
|
}
|
|
}
|
|
|
|
static void
|
|
cg4a_ldcmap(sc)
|
|
struct cg4_softc *sc;
|
|
{
|
|
volatile struct amd_regs *ar = sc->sc_va_cmap;
|
|
struct soft_cmap *cm = &sc->sc_cmap;
|
|
int i;
|
|
|
|
/*
|
|
* Now blast them into the chip!
|
|
* XXX Should use retrace interrupt!
|
|
* Just set a "need load" bit and let the
|
|
* retrace interrupt handler do the work.
|
|
*/
|
|
if (sc->sc_video_on) {
|
|
/* Update H/W colormap. */
|
|
for (i = 0; i < 256; i++) {
|
|
ar->r[i] = cm->r[i];
|
|
ar->g[i] = cm->g[i];
|
|
ar->b[i] = cm->b[i];
|
|
}
|
|
} else {
|
|
/* Clear H/W colormap. */
|
|
for (i = 0; i < 256; i++) {
|
|
ar->r[i] = 0;
|
|
ar->g[i] = 0;
|
|
ar->b[i] = 0;
|
|
}
|
|
}
|
|
}
|
|
#endif /* SUN3 */
|
|
|
|
/****************************************************************
|
|
* Routines for the "Type B" hardware
|
|
****************************************************************/
|
|
|
|
static void
|
|
cg4b_init(sc)
|
|
struct cg4_softc *sc;
|
|
{
|
|
volatile struct bt_regs *bt = sc->sc_va_cmap;
|
|
struct soft_cmap *cm = &sc->sc_cmap;
|
|
union bt_cmap_u *btcm;
|
|
int i;
|
|
|
|
/* Need a buffer for colormap format translation. */
|
|
btcm = malloc(sizeof(*btcm), M_DEVBUF, M_WAITOK);
|
|
sc->sc_btcm = btcm;
|
|
|
|
/*
|
|
* BT458 chip initialization as described in Brooktree's
|
|
* 1993 Graphics and Imaging Product Databook (DB004-1/93).
|
|
*
|
|
* It appears that the 3/60 uses the low byte, and the 3/80
|
|
* uses the high byte, while both ignore the other bytes.
|
|
* Writing same value to all bytes works on both.
|
|
*/
|
|
bt->bt_addr = 0x04040404; /* select read mask register */
|
|
bt->bt_ctrl = ~0; /* all planes on */
|
|
bt->bt_addr = 0x05050505; /* select blink mask register */
|
|
bt->bt_ctrl = 0; /* all planes non-blinking */
|
|
bt->bt_addr = 0x06060606; /* select command register */
|
|
bt->bt_ctrl = 0x43434343; /* palette enabled, overlay planes enabled */
|
|
bt->bt_addr = 0x07070707; /* select test register */
|
|
bt->bt_ctrl = 0; /* not test mode */
|
|
|
|
/* grab initial (current) color map */
|
|
bt->bt_addr = 0;
|
|
#ifdef _SUN3_
|
|
/* Sun3/60 wants 32-bit access, packed. */
|
|
for (i = 0; i < (256 * 3 / 4); i++)
|
|
btcm->btcm_int[i] = bt->bt_cmap;
|
|
#else /* SUN3 */
|
|
/* Sun3/80 wants 8-bits in the high byte. */
|
|
for (i = 0; i < (256 * 3); i++)
|
|
btcm->btcm_char[i] = bt->bt_cmap >> 24;
|
|
#endif /* SUN3 */
|
|
|
|
/* Transpose into H/W cmap into S/W form. */
|
|
for (i = 0; i < 256; i++) {
|
|
cm->r[i] = btcm->btcm_rgb[i][0];
|
|
cm->g[i] = btcm->btcm_rgb[i][1];
|
|
cm->b[i] = btcm->btcm_rgb[i][2];
|
|
}
|
|
}
|
|
|
|
static void
|
|
cg4b_ldcmap(sc)
|
|
struct cg4_softc *sc;
|
|
{
|
|
volatile struct bt_regs *bt = sc->sc_va_cmap;
|
|
struct soft_cmap *cm = &sc->sc_cmap;
|
|
union bt_cmap_u *btcm = sc->sc_btcm;
|
|
int i;
|
|
|
|
/* Transpose S/W cmap into H/W form. */
|
|
for (i = 0; i < 256; i++) {
|
|
btcm->btcm_rgb[i][0] = cm->r[i];
|
|
btcm->btcm_rgb[i][1] = cm->g[i];
|
|
btcm->btcm_rgb[i][2] = cm->b[i];
|
|
}
|
|
|
|
/*
|
|
* Now blast them into the chip!
|
|
* XXX Should use retrace interrupt!
|
|
* Just set a "need load" bit and let the
|
|
* retrace interrupt handler do the work.
|
|
*/
|
|
bt->bt_addr = 0;
|
|
|
|
#ifdef _SUN3_
|
|
/* Sun3/60 wants 32-bit access, packed. */
|
|
if (sc->sc_video_on) {
|
|
/* Update H/W colormap. */
|
|
for (i = 0; i < (256 * 3 / 4); i++)
|
|
bt->bt_cmap = btcm->btcm_int[i];
|
|
} else {
|
|
/* Clear H/W colormap. */
|
|
for (i = 0; i < (256 * 3 / 4); i++)
|
|
bt->bt_cmap = 0;
|
|
}
|
|
#else /* SUN3 */
|
|
/* Sun3/80 wants 8-bits in the high byte. */
|
|
if (sc->sc_video_on) {
|
|
/* Update H/W colormap. */
|
|
for (i = 0; i < (256 * 3); i++)
|
|
bt->bt_cmap = btcm->btcm_char[i] << 24;
|
|
} else {
|
|
/* Clear H/W colormap. */
|
|
for (i = 0; i < (256 * 3); i++)
|
|
bt->bt_cmap = 0;
|
|
}
|
|
#endif /* SUN3 */
|
|
}
|
|
|