pk 52d6871979 Use ic_*' cacheinfo fields, and in the split-I&D case, derive c_linesize[l2]' ... from from the corresponding `ic_*' and `dc_*' values. This is not perfect, but it makes SS4s and SS5s run until we have proper per-cpu cache handling. Use the `cache-physical?' property to determine the value of `vactype' on sun4m's. If absent, set vactype to VAC_WRITETHROUGH (XXX) else VAC_NONE. Print simpler sun4m CPU identifier on attach.		1996-06-12 14:56:09 +00:00
..
compile	compile needs to be kept in the distribution	1993-04-19 23:30:06 +00:00
conf	Switch to `sys/dev/sun/event.c'.	1996-05-29 21:56:38 +00:00
dev	Correct test for dmachild' which failed on esp at obio*' configs (PR#2541).	1996-06-12 12:46:21 +00:00
fpu	Add and bring prototypes into scope.	1996-03-14 19:41:49 +00:00
include	prototype mmu_pagein4m() #if DEBUG is on.	1996-05-27 20:29:03 +00:00
sparc	Use ic_*' cacheinfo fields, and in the split-I&D case, derive c_linesize[l2]'	1996-06-12 14:56:09 +00:00
stand	Enable just enough interrupts to get "L1-A" through. Patch from Jason to	1996-05-23 22:35:11 +00:00
Makefile	sync with reality.	1996-05-24 23:18:23 +00:00