194 lines
6.1 KiB
C
194 lines
6.1 KiB
C
/* $NetBSD: stpcide.c,v 1.11 2004/08/21 21:46:54 nisimura Exp $ */
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/*
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* Copyright (c) 2003 Tohru Nishimura
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Tohru Nishimura.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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static void stpc_chip_map(struct pciide_softc *, struct pci_attach_args *);
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static void stpc_setup_channel(struct ata_channel *);
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static int stpcide_match(struct device *, struct cfdata *, void *);
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static void stpcide_attach(struct device *, struct device *, void *);
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const struct pciide_product_desc pciide_stpc_products[] = {
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{ 0x0228,
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0,
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"STMicroelectronics STPC IDE Controller",
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stpc_chip_map,
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},
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{ 0, 0, NULL, NULL },
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};
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CFATTACH_DECL(stpcide, sizeof(struct pciide_softc),
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stpcide_match, stpcide_attach, NULL, NULL);
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static int
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stpcide_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SGSTHOMSON) {
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if (pciide_lookup_product(pa->pa_id, pciide_stpc_products))
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return (2);
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}
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return (0);
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}
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static void
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stpcide_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_stpc_products));
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}
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static void
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stpc_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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int channel;
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pcireg_t interface = PCI_INTERFACE(pa->pa_class);
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bus_size_t cmdsize, ctlsize;
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if (pciide_chipen(sc, pa) == 0)
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return;
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aprint_normal("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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pciide_mapreg_dma(sc, pa);
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aprint_normal("\n");
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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}
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 0;
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sc->sc_wdcdev.sc_atac.atac_set_modes = stpc_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
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wdc_allocate_regs(&sc->sc_wdcdev);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
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pciide_pci_intr);
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}
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}
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/*
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* IDE timing register (0x40, 0x42, 0x44, and 0x46) assignment.
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* 33MHz PCI system will have;
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* DMA0 01-11-11
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* DMA1 00-01-10
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* DMA2 00-00-10
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* PIO0 111-100
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* PIO1 100-011
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* PIO2 011-010
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* PIO3 010-001
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* PIO4 000-001
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* MISC XYZW
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*/
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static const u_int16_t dmatbl[] = { 0x7C00, 0x1800, 0x0800 };
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static const u_int16_t piotbl[] = { 0x03C0, 0x0230, 0x01A0, 0x0110, 0x0010 };
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static void
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stpc_setup_channel(struct ata_channel *chp)
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{
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struct atac_softc *atac = chp->ch_atac;
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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int channel = chp->ch_channel;
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struct ata_drive_datas *drvp;
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u_int32_t idedma_ctl, idetim;
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int drive, bits[2], s;
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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idedma_ctl = 0;
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bits[0] = bits[1] = 0x7F60; /* assume PIO2/DMA0 */
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/* Per drive settings */
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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/* add timing values, setup DMA if needed */
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if ((atac->atac_cap & ATAC_CAP_DMA) &&
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(drvp->drive_flags & DRIVE_DMA)) {
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/* use Multiword DMA */
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s = splbio();
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drvp->drive_flags &= ~DRIVE_UDMA;
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splx(s);
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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bits[drive] = 0xe; /* IOCHRDY,wr/post,rd/prefetch */
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}
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else {
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/* PIO only */
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s = splbio();
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drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA);
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splx(s);
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bits[drive] = 0x8; /* IOCHRDY */
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}
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bits[drive] |= dmatbl[drvp->DMA_mode] | piotbl[drvp->PIO_mode];
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}
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#if 0
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idetim = pci_conf_read(sc->sc_pc, sc->sc_tag,
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(channel == 0) ? 0x40 : 0x44);
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aprint_normal("wdc%d: IDETIM %08x -> %08x\n",
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channel, idetim, (bits[1] << 16) | bits[0]);
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#endif
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idetim = (bits[1] << 16) | bits[0];
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pci_conf_write(sc->sc_pc, sc->sc_tag,
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(channel == 0) ? 0x40 : 0x44, idetim);
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if (idedma_ctl != 0) {
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/* Add software bits in status register */
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bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
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idedma_ctl);
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}
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}
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