427 lines
12 KiB
C
427 lines
12 KiB
C
/* $NetBSD: if_iwireg.h,v 1.2 2005/01/11 18:49:05 skrll Exp $ */
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/*-
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* Copyright (c) 2004, 2005
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* Damien Bergamini <damien.bergamini@free.fr>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#define IWI_TX_RING_SIZE 64
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#define IWI_CMD_RING_SIZE 16
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#define IWI_RX_RING_SIZE 32
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#define IWI_CSR_INTR 0x0008
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#define IWI_CSR_INTR_MASK 0x000c
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#define IWI_CSR_INDIRECT_ADDR 0x0010
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#define IWI_CSR_INDIRECT_DATA 0x0014
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#define IWI_CSR_AUTOINC_ADDR 0x0018
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#define IWI_CSR_AUTOINC_DATA 0x001c
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#define IWI_CSR_RST 0x0020
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#define IWI_CSR_CTL 0x0024
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#define IWI_CSR_IO 0x0030
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#define IWI_CSR_CMD_BASE 0x0200
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#define IWI_CSR_CMD_SIZE 0x0204
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#define IWI_CSR_TX1_BASE 0x0208
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#define IWI_CSR_TX1_SIZE 0x020c
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#define IWI_CSR_TX2_BASE 0x0210
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#define IWI_CSR_TX2_SIZE 0x0214
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#define IWI_CSR_TX3_BASE 0x0218
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#define IWI_CSR_TX3_SIZE 0x021c
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#define IWI_CSR_TX4_BASE 0x0220
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#define IWI_CSR_TX4_SIZE 0x0224
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#define IWI_CSR_CMD_READ_INDEX 0x0280
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#define IWI_CSR_TX1_READ_INDEX 0x0284
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#define IWI_CSR_TX2_READ_INDEX 0x0288
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#define IWI_CSR_TX3_READ_INDEX 0x028c
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#define IWI_CSR_TX4_READ_INDEX 0x0290
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#define IWI_CSR_RX_READ_INDEX 0x02a0
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#define IWI_CSR_RX_BASE 0x0500
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#define IWI_CSR_TABLE0_SIZE 0x0700
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#define IWI_CSR_TABLE0_BASE 0x0704
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#define IWI_CSR_CURRENT_TX_RATE IWI_CSR_TABLE0_BASE
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#define IWI_CSR_CMD_WRITE_INDEX 0x0f80
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#define IWI_CSR_TX1_WRITE_INDEX 0x0f84
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#define IWI_CSR_TX2_WRITE_INDEX 0x0f88
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#define IWI_CSR_TX3_WRITE_INDEX 0x0f8c
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#define IWI_CSR_TX4_WRITE_INDEX 0x0f90
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#define IWI_CSR_RX_WRITE_INDEX 0x0fa0
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#define IWI_CSR_READ_INT 0x0ff4
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/* possible flags for IWI_CSR_INTR */
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#define IWI_INTR_RX_TRANSFER 0x00000002
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#define IWI_INTR_CMD_TRANSFER 0x00000800
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#define IWI_INTR_TX1_TRANSFER 0x00001000
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#define IWI_INTR_TX2_TRANSFER 0x00002000
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#define IWI_INTR_TX3_TRANSFER 0x00004000
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#define IWI_INTR_TX4_TRANSFER 0x00008000
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#define IWI_INTR_FW_INITED 0x01000000
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#define IWI_INTR_RADIO_OFF 0x04000000
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#define IWI_INTR_FATAL_ERROR 0x40000000
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#define IWI_INTR_PARITY_ERROR 0x80000000
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#define IWI_INTR_MASK \
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(IWI_INTR_RX_TRANSFER | IWI_INTR_CMD_TRANSFER | \
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IWI_INTR_TX1_TRANSFER | IWI_INTR_TX2_TRANSFER | \
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IWI_INTR_TX3_TRANSFER | IWI_INTR_TX4_TRANSFER | \
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IWI_INTR_FW_INITED | IWI_INTR_RADIO_OFF | \
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IWI_INTR_FATAL_ERROR | IWI_INTR_PARITY_ERROR)
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/* possible flags for register IWI_CSR_RST */
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#define IWI_RST_PRINCETON_RESET 0x00000001
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#define IWI_RST_SW_RESET 0x00000080
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#define IWI_RST_MASTER_DISABLED 0x00000100
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#define IWI_RST_STOP_MASTER 0x00000200
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/* possible flags for register IWI_CSR_CTL */
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#define IWI_CTL_CLOCK_READY 0x00000001
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#define IWI_CTL_ALLOW_STANDBY 0x00000002
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#define IWI_CTL_INIT 0x00000004
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/* possible flags for register IWI_CSR_IO */
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#define IWI_IO_RADIO_ENABLED 0x00010000
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/* possible flags for IWI_CSR_READ_INT */
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#define IWI_READ_INT_INIT_HOST 0x20000000
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/* table2 offsets */
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#define IWI_INFO_ADAPTER_MAC 40
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/* constants for command blocks */
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#define IWI_CB_DEFAULT_CTL 0x8cea0000
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#define IWI_CB_MAXDATALEN 8191
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/* supported rates */
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#define IWI_RATE_DS1 10
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#define IWI_RATE_DS2 20
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#define IWI_RATE_DS5 55
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#define IWI_RATE_DS11 110
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#define IWI_RATE_OFDM6 13
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#define IWI_RATE_OFDM9 15
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#define IWI_RATE_OFDM12 5
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#define IWI_RATE_OFDM18 7
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#define IWI_RATE_OFDM24 9
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#define IWI_RATE_OFDM36 11
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#define IWI_RATE_OFDM48 1
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#define IWI_RATE_OFDM54 3
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struct iwi_hdr {
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u_int8_t type;
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#define IWI_HDR_TYPE_DATA 0
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#define IWI_HDR_TYPE_COMMAND 1
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#define IWI_HDR_TYPE_NOTIF 3
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#define IWI_HDR_TYPE_FRAME 9
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u_int8_t seq;
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u_int8_t flags;
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#define IWI_HDR_FLAG_IRQ 0x04
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u_int8_t reserved;
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} __attribute__((__packed__));
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struct iwi_notif {
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u_int32_t reserved[2];
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u_int8_t type;
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#define IWI_NOTIF_TYPE_ASSOCIATION 10
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#define IWI_NOTIF_TYPE_AUTHENTICATION 11
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#define IWI_NOTIF_TYPE_SCAN_CHANNEL 12
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#define IWI_NOTIF_TYPE_SCAN_COMPLETE 13
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#define IWI_NOTIF_TYPE_BEACON 17
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#define IWI_NOTIF_TYPE_CALIBRATION 20
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#define IWI_NOTIF_TYPE_NOISE 25
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u_int8_t flags;
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u_int16_t len;
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} __attribute__((__packed__));
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/* structure for notification IWI_NOTIF_TYPE_AUTHENTICATION */
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struct iwi_notif_authentication {
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u_int8_t state;
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#define IWI_DEAUTHENTICATED 0
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#define IWI_AUTHENTICATED 9
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} __attribute__((__packed__));
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/* structure for notification IWI_NOTIF_TYPE_ASSOCIATION */
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struct iwi_notif_association {
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u_int8_t state;
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#define IWI_DEASSOCIATED 0
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#define IWI_ASSOCIATED 12
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struct ieee80211_frame frame;
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u_int16_t capinfo;
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u_int16_t status;
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u_int16_t associd;
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} __attribute__((__packed__));
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/* structure for notification IWI_NOTIF_TYPE_SCAN_CHANNEL */
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struct iwi_notif_scan_channel {
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u_int8_t nchan;
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u_int8_t reserved[47];
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} __attribute__((__packed__));
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/* structure for notification IWI_NOTIF_TYPE_SCAN_COMPLETE */
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struct iwi_notif_scan_complete {
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u_int8_t type;
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u_int8_t nchan;
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u_int8_t status;
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u_int8_t reserved;
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} __attribute__((__packed__));
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/* received frame header */
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struct iwi_frame {
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u_int32_t reserved1[2];
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u_int8_t chan;
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u_int8_t status;
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u_int8_t rate;
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u_int8_t rssi; /* receiver signal strength indicator */
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u_int8_t agc; /* automatic gain control */
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u_int8_t rssi_dbm;
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u_int16_t signal;
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u_int16_t noise;
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u_int8_t antenna;
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u_int8_t control;
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u_int8_t reserved2[2];
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u_int16_t len;
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} __attribute__((__packed__));
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/* header for transmission */
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struct iwi_tx_desc {
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struct iwi_hdr hdr;
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u_int32_t reserved1[2];
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u_int8_t cmd;
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#define IWI_DATA_CMD_TX 0x0b
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u_int8_t seq;
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u_int16_t len;
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u_int8_t priority;
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u_int8_t flags;
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#define IWI_DATA_FLAG_SHPREAMBLE 0x04
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#define IWI_DATA_FLAG_NO_WEP 0x20
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#define IWI_DATA_FLAG_NEED_ACK 0x80
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u_int8_t xflags;
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u_int8_t wep_txkey;
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u_int8_t wepkey[IEEE80211_KEYBUF_SIZE];
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u_int8_t rate;
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u_int8_t antenna;
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u_int8_t reserved2[10];
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struct ieee80211_qosframe_addr4 wh;
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u_int32_t iv[2];
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u_int32_t nseg;
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#define IWI_MAX_NSEG 6
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u_int32_t seg_addr[IWI_MAX_NSEG];
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u_int16_t seg_len[IWI_MAX_NSEG];
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} __attribute__((__packed__));
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/* command */
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struct iwi_cmd_desc {
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struct iwi_hdr hdr;
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u_int8_t type;
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#define IWI_CMD_ENABLE 2
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#define IWI_CMD_SET_CONFIGURATION 6
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#define IWI_CMD_SET_ESSID 8
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#define IWI_CMD_SET_MAC_ADDRESS 11
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#define IWI_CMD_SET_RTS_THRESHOLD 15
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#define IWI_CMD_SET_POWER_MODE 17
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#define IWI_CMD_SET_WEP_KEY 18
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#define IWI_CMD_SCAN 20
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#define IWI_CMD_ASSOCIATE 21
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#define IWI_CMD_SET_RATES 22
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#define IWI_CMD_DISABLE 33
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#define IWI_CMD_SET_IV 34
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#define IWI_CMD_SET_TX_POWER 35
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#define IWI_CMD_SET_SENSITIVITY 42
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u_int8_t len;
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u_int16_t reserved;
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u_int8_t data[120];
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} __attribute__((__packed__));
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/* constants for 'mode' fields */
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#define IWI_MODE_11A 0
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#define IWI_MODE_11B 1
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#define IWI_MODE_11G 2
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/* macro for command IWI_CMD_SET_SENSITIVITY */
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#define IWI_RSSIDBM2RAW(rssi) ((rssi) - 112)
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/* possible values for command IWI_CMD_SET_POWER_MODE */
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#define IWI_POWER_MODE_CAM 0
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/* structure for command IWI_CMD_SET_RATES */
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struct iwi_rateset {
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u_int8_t mode;
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u_int8_t nrates;
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u_int8_t type;
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#define IWI_RATESET_TYPE_NEGOCIATED 0
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#define IWI_RATESET_TYPE_SUPPORTED 1
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u_int8_t reserved;
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u_int8_t rates[12];
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} __attribute__((__packed__));
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/* structure for command IWI_CMD_SET_TX_POWER */
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struct iwi_txpower {
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u_int8_t nchan;
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u_int8_t mode;
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struct {
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u_int8_t chan;
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u_int8_t power;
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#define IWI_TXPOWER_MAX 20
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#define IWI_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IWI_TXPOWER_MAX)
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} __attribute__((__packed__)) chan[37];
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} __attribute__((__packed__));
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/* structure for command IWI_CMD_ASSOCIATE */
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struct iwi_associate {
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u_int8_t chan;
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u_int8_t auth;
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#define IWI_AUTH_OPEN 0
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#define IWI_AUTH_SHARED 1
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#define IWI_AUTH_NONE 3
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u_int8_t type;
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u_int8_t reserved1;
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u_int16_t reserved2;
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u_int8_t plen;
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u_int8_t mode;
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u_int8_t bssid[IEEE80211_ADDR_LEN];
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u_int8_t tstamp[8];
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u_int16_t capinfo;
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u_int16_t lintval;
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u_int16_t intval;
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u_int8_t dst[IEEE80211_ADDR_LEN];
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u_int32_t reserved3;
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u_int16_t reserved4;
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} __attribute__((__packed__));
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/* structure for command IWI_CMD_SCAN */
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struct iwi_scan {
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u_int8_t type;
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#define IWI_SCAN_TYPE_BROADCAST 3
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u_int16_t intval;
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u_int8_t channels[54];
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#define IWI_CHAN_5GHZ (0 << 6)
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#define IWI_CHAN_2GHZ (1 << 6)
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u_int8_t reserved[3];
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} __attribute__((__packed__));
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/* structure for command IWI_CMD_SET_CONFIGURATION */
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struct iwi_configuration {
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u_int8_t bluetooth_coexistence;
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u_int8_t reserved1;
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u_int8_t answer_broadcast_probe_req;
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u_int8_t allow_invalid_frames;
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u_int8_t multicast_enabled;
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u_int8_t exclude_unicast_unencrypted;
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u_int8_t disable_unicast_decryption;
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u_int8_t exclude_multicast_unencrypted;
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u_int8_t disable_multicast_decryption;
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u_int8_t antenna;
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u_int8_t reserved2;
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u_int8_t bg_autodetection;
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u_int8_t reserved3;
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u_int8_t enable_multicast_filtering;
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u_int8_t bluetooth_threshold;
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u_int8_t reserved4;
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u_int8_t allow_beacon_and_probe_resp;
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u_int8_t allow_mgt;
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u_int8_t noise_reported;
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u_int8_t reserved5;
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} __attribute__((__packed__));
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/* structure for command IWI_CMD_SET_WEP_KEY */
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struct iwi_wep_key {
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u_int8_t cmd;
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#define IWI_WEP_KEY_CMD_SETKEY 0x08
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u_int8_t seq;
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u_int8_t idx;
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u_int8_t len;
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u_int8_t key[IEEE80211_KEYBUF_SIZE];
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} __attribute__((__packed__));
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/* EEPROM = Electrically Erasable Programmable Read-Only Memory */
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#define IWI_MEM_EEPROM_CTL 0x00300040
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#define IWI_EEPROM_MAC 0x21
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#define IWI_EEPROM_DELAY 1 /* minimum hold time (microsecond) */
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#define IWI_EEPROM_C (1 << 0) /* Serial Clock */
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#define IWI_EEPROM_S (1 << 1) /* Chip Select */
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#define IWI_EEPROM_D (1 << 2) /* Serial data input */
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#define IWI_EEPROM_Q (1 << 4) /* Serial data output */
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#define IWI_EEPROM_SHIFT_D 2
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#define IWI_EEPROM_SHIFT_Q 4
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/*
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* control and status registers access macros
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*/
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
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#define CSR_READ_REGION_4(sc, offset, datap, count) \
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bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \
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(datap), (count))
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
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/*
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* indirect memory space access macros
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*/
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#define MEM_WRITE_1(sc, addr, val) do { \
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CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
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CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
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} while (/* CONSTCOND */0)
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#define MEM_WRITE_2(sc, addr, val) do { \
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CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
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CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
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} while (/* CONSTCOND */0)
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#define MEM_WRITE_4(sc, addr, val) do { \
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CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
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CSR_WRITE_4((sc), IWI_CSR_INDIRECT_DATA, (val)); \
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} while (/* CONSTCOND */0)
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#define MEM_WRITE_MULTI_1(sc, addr, buf, len) do { \
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CSR_WRITE_4((sc), IWI_CSR_INDIRECT_ADDR, (addr)); \
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CSR_WRITE_MULTI_1((sc), IWI_CSR_INDIRECT_DATA, (buf), (len)); \
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} while (/* CONSTCOND */0)
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/*
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* EEPROM access macro
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*/
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#define IWI_EEPROM_CTL(sc, val) do { \
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MEM_WRITE_4((sc), IWI_MEM_EEPROM_CTL, (val)); \
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DELAY(IWI_EEPROM_DELAY); \
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} while (/* CONSTCOND */0)
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