409 lines
12 KiB
C
409 lines
12 KiB
C
/* $NetBSD: hptide.c,v 1.16 2004/08/21 00:28:34 thorpej Exp $ */
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/*
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* Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_hpt_reg.h>
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static void hpt_chip_map(struct pciide_softc*, struct pci_attach_args*);
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static void hpt_setup_channel(struct ata_channel*);
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static int hpt_pci_intr(void *);
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static int hptide_match(struct device *, struct cfdata *, void *);
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static void hptide_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(hptide, sizeof(struct pciide_softc),
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hptide_match, hptide_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_triones_products[] = {
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{ PCI_PRODUCT_TRIONES_HPT302,
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0,
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NULL,
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hpt_chip_map
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},
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{ PCI_PRODUCT_TRIONES_HPT366,
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0,
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NULL,
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hpt_chip_map,
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},
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{ PCI_PRODUCT_TRIONES_HPT371,
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0,
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NULL,
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hpt_chip_map,
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},
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{ PCI_PRODUCT_TRIONES_HPT372A,
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0,
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NULL,
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hpt_chip_map
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},
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{ PCI_PRODUCT_TRIONES_HPT374,
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0,
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NULL,
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hpt_chip_map
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static int
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hptide_match(struct device *parent, struct cfdata *match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TRIONES) {
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if (pciide_lookup_product(pa->pa_id, pciide_triones_products))
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return (2);
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}
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return (0);
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}
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static void
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hptide_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_triones_products));
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}
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static void
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hpt_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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int i, compatchan, revision;
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pcireg_t interface;
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bus_size_t cmdsize, ctlsize;
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if (pciide_chipen(sc, pa) == 0)
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return;
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revision = PCI_REVISION(pa->pa_class);
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aprint_normal("%s: Triones/Highpoint ",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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switch (sc->sc_pp->ide_product) {
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case PCI_PRODUCT_TRIONES_HPT302:
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aprint_normal("HPT302 IDE Controller\n");
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break;
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case PCI_PRODUCT_TRIONES_HPT371:
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aprint_normal("HPT371 IDE Controller\n");
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break;
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case PCI_PRODUCT_TRIONES_HPT374:
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aprint_normal("HPT374 IDE Controller\n");
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break;
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case PCI_PRODUCT_TRIONES_HPT372A:
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aprint_normal("HPT372A IDE Controller\n");
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break;
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case PCI_PRODUCT_TRIONES_HPT366:
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if (revision == HPT372_REV)
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aprint_normal("HPT372 IDE Controller\n");
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else if (revision == HPT370_REV)
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aprint_normal("HPT370 IDE Controller\n");
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else if (revision == HPT370A_REV)
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aprint_normal("HPT370A IDE Controller\n");
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else if (revision == HPT366_REV)
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aprint_normal("HPT366 IDE Controller\n");
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else
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aprint_normal("unknown HPT IDE controller rev %d\n",
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revision);
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break;
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default:
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aprint_normal("unknown HPT IDE controller 0x%x\n",
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sc->sc_pp->ide_product);
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}
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/*
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* when the chip is in native mode it identifies itself as a
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* 'misc mass storage'. Fake interface in this case.
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*/
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if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
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interface = PCI_INTERFACE(pa->pa_class);
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} else {
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interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
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PCIIDE_INTERFACE_PCI(0);
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if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
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(revision == HPT370_REV || revision == HPT370A_REV ||
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revision == HPT372_REV)) ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
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interface |= PCIIDE_INTERFACE_PCI(1);
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}
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aprint_normal("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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pciide_mapreg_dma(sc, pa);
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aprint_normal("\n");
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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}
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_set_modes = hpt_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
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revision == HPT366_REV) {
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sc->sc_wdcdev.sc_atac.atac_nchannels = 1;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
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} else {
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sc->sc_wdcdev.sc_atac.atac_nchannels = 2;
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if (sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374 ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
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(sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
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revision == HPT372_REV))
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
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else
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
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}
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wdc_allocate_regs(&sc->sc_wdcdev);
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for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
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cp = &sc->pciide_channels[i];
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if (sc->sc_wdcdev.sc_atac.atac_nchannels > 1) {
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compatchan = i;
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if((pciide_pci_read(sc->sc_pc, sc->sc_tag,
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HPT370_CTRL1(i)) & HPT370_CTRL1_EN) == 0) {
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aprint_normal(
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"%s: %s channel ignored (disabled)\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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cp->ata_channel.ch_flags |= ATACH_DISABLED;
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continue;
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}
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} else {
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/*
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* The 366 has 2 PCI IDE functions, one for primary and
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* one for secondary. So we need to call
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* pciide_mapregs_compat() with the real channel.
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*/
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if (pa->pa_function == 0)
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compatchan = 0;
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else if (pa->pa_function == 1)
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compatchan = 1;
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else {
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aprint_error("%s: unexpected PCI function %d\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, pa->pa_function);
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return;
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}
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}
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if (pciide_chansetup(sc, i, interface) == 0)
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continue;
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if (interface & PCIIDE_INTERFACE_PCI(i)) {
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pciide_mapregs_native(pa, cp, &cmdsize,
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&ctlsize, hpt_pci_intr);
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} else {
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pciide_mapregs_compat(pa, cp, compatchan,
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&cmdsize, &ctlsize);
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if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
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pciide_map_compat_intr(pa, cp,
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sc->sc_cy_compatchan);
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}
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wdcattach(&cp->ata_channel);
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}
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if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
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(revision == HPT370_REV || revision == HPT370A_REV ||
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revision == HPT372_REV)) ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374) {
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/*
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* HPT370_REV and highter has a bit to disable interrupts,
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* make sure to clear it
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*/
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pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_CSEL,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL) &
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~HPT_CSEL_IRQDIS);
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}
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/* set clocks, etc (mandatory on 372/4, optional otherwise) */
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if ((sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT366 &&
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revision == HPT372_REV ) ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT302 ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT371 ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT372A ||
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sc->sc_pp->ide_product == PCI_PRODUCT_TRIONES_HPT374)
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pciide_pci_write(sc->sc_pc, sc->sc_tag, HPT_SC2,
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(pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_SC2) &
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HPT_SC2_MAEN) | HPT_SC2_OSC_EN);
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return;
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}
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static void
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hpt_setup_channel(struct ata_channel *chp)
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{
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struct ata_drive_datas *drvp;
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int drive, s;
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int cable;
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u_int32_t before, after;
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u_int32_t idedma_ctl;
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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int revision =
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PCI_REVISION(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG));
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const u_int32_t *tim_pio, *tim_dma, *tim_udma;
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cable = pciide_pci_read(sc->sc_pc, sc->sc_tag, HPT_CSEL);
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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idedma_ctl = 0;
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/* select the timing arrays for the chip */
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switch (sc->sc_pp->ide_product) {
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case PCI_PRODUCT_TRIONES_HPT374:
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tim_udma = hpt374_udma;
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tim_dma = hpt374_dma;
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tim_pio = hpt374_pio;
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break;
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case PCI_PRODUCT_TRIONES_HPT302:
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case PCI_PRODUCT_TRIONES_HPT371:
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case PCI_PRODUCT_TRIONES_HPT372A:
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tim_udma = hpt372_udma;
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tim_dma = hpt372_dma;
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tim_pio = hpt372_pio;
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break;
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case PCI_PRODUCT_TRIONES_HPT366:
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default:
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switch (revision) {
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case HPT372_REV:
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tim_udma = hpt372_udma;
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tim_dma = hpt372_dma;
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tim_pio = hpt372_pio;
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break;
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case HPT370_REV:
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case HPT370A_REV:
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tim_udma = hpt370_udma;
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tim_dma = hpt370_dma;
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tim_pio = hpt370_pio;
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break;
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case HPT366_REV:
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default:
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tim_udma = hpt366_udma;
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tim_dma = hpt366_dma;
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tim_pio = hpt366_pio;
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break;
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}
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}
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/* Per drive settings */
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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before = pci_conf_read(sc->sc_pc, sc->sc_tag,
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HPT_IDETIM(chp->ch_channel, drive));
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/* add timing values, setup DMA if needed */
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if (drvp->drive_flags & DRIVE_UDMA) {
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/* use Ultra/DMA */
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s = splbio();
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drvp->drive_flags &= ~DRIVE_DMA;
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splx(s);
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if ((cable & HPT_CSEL_CBLID(chp->ch_channel)) != 0 &&
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drvp->UDMA_mode > 2)
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drvp->UDMA_mode = 2;
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after = tim_udma[drvp->UDMA_mode];
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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} else if (drvp->drive_flags & DRIVE_DMA) {
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/*
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* use Multiword DMA.
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* Timings will be used for both PIO and DMA, so adjust
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* DMA mode if needed
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*/
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if (drvp->PIO_mode >= 3 &&
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(drvp->DMA_mode + 2) > drvp->PIO_mode) {
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drvp->DMA_mode = drvp->PIO_mode - 2;
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}
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after = tim_dma[drvp->DMA_mode];
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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} else {
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/* PIO only */
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after = tim_pio[drvp->PIO_mode];
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}
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pci_conf_write(sc->sc_pc, sc->sc_tag,
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HPT_IDETIM(chp->ch_channel, drive), after);
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ATADEBUG_PRINT(("%s: bus speed register set to 0x%08x "
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"(BIOS 0x%08x)\n", drvp->drv_softc->dv_xname,
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after, before), DEBUG_PROBE);
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}
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if (idedma_ctl != 0) {
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/* Add software bits in status register */
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bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
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idedma_ctl);
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}
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}
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static int
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hpt_pci_intr(void *arg)
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{
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struct pciide_softc *sc = arg;
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struct pciide_channel *cp;
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struct ata_channel *wdc_cp;
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int rv = 0;
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int dmastat, i, crv;
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for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
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cp = &sc->pciide_channels[i];
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dmastat = bus_space_read_1(sc->sc_dma_iot,
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cp->dma_iohs[IDEDMA_CTL], 0);
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if((dmastat & ( IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) !=
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IDEDMA_CTL_INTR)
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continue;
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wdc_cp = &cp->ata_channel;
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crv = wdcintr(wdc_cp);
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if (crv == 0) {
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printf("%s:%d: bogus intr\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i);
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bus_space_write_1(sc->sc_dma_iot,
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cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
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} else
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rv = 1;
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}
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return rv;
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}
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