281 lines
13 KiB
C
281 lines
13 KiB
C
/* $NetBSD: cs4281reg.h,v 1.4 2005/01/15 15:19:52 kent Exp $ */
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/*
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* Copyright (c) 2000 Tatoku Ogaito. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Tatoku Ogaito
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define CS4281_BA0_SIZE
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#define CS4281_BA1_SIZE 0x10000
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#define CS4281_BUFFER_SIZE 0x10000
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/* Base Address 0 */
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/* Interrupt Reporting Registers */
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#define CS4281_HISR 0x000 /* Host Interrupt Status Register*/
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#define HISR_INTENA 0x80000000
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#define HISR_MIDI 0x00400000
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#define HISR_FIFOI 0x00100000
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#define HISR_DMAI 0x00040000
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#define HISR_FIFO3 0x00008000
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#define HISR_FIFO2 0x00004000
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#define HISR_FIFO1 0x00002000
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#define HISR_FIFO0 0x00001000
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#define HISR_DMA3 0x00000800
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#define HISR_DMA2 0x00000400
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#define HISR_DMA1 0x00000200
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#define HISR_DMA0 0x00000100
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#define HISR_GPPI 0x00000020
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#define HISR_GPSI 0x00000010
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#define HISR_GP3I 0x00000008
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#define HISR_GP1I 0x00000004
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#define HISR_VUPI 0x00000002
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#define HISR_VDNI 0x00000001
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#define CS4281_HICR 0x008 /* Host Interrupt Control Register */
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#define HICR_CHGM 0x00000002
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#define HICR_IEV 0x00000001
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#define CS4281_HIMR 0x00C /* Host Interrupt Mask Register */
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#define HIMR_MIDIM 0x00400000
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#define HIMR_FIFOIM 0x00100000
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#define HIMR_DMAIM 0x00040000
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#define HIMR_F3IM 0x00008000
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#define HIMR_F2IM 0x00004000
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#define HIMR_F1IM 0x00002000
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#define HIMR_F0IM 0x00001000
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#define HIMR_D3IM 0x00000800
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#define HIMR_D2IM 0x00000400
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#define HIMR_D1IM 0x00000200
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#define HIMR_D0IM 0x00000100
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#define HIMR_GPPIM 0x00000020
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#define HIMR_GPSIM 0x00000010
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#define HIMR_GP3IM 0x00000008
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#define HIMR_GP1IM 0x00000004
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#define HIMR_VUPIM 0x00000002
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#define HIMR_VDNIM 0x00000001
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#define CS4281_IIER 0x010 /* ISA Interrupt Enable Register */
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#define CS4281_HDSR0 0x0F0 /* Host DMA Engine 0 Status Register */
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#define CS4281_HDSR1 0x0F4 /* Host DMA Engine 1 Status Register */
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#define CS4281_HDSR2 0x0F8 /* Host DMA Engine 2 Status Register */
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#define CS4281_HDSR3 0x0FC /* Host DMA Engine 3 Status Register */
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#define CS4281_DCA0 0x110 /* DMA Engine 0 Current Address Register */
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#define CS4281_DCC0 0x114 /* DMA Engine 0 Current Count Register */
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#define CS4281_DBA0 0x118 /* DMA Engine 0 Base Address Register */
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#define CS4281_DBC0 0x11C /* DMA Engine 0 Base Count Register */
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#define CS4281_DCA1 0x120 /* DMA Engine 1 Current Address Register */
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#define CS4281_DCC1 0x124 /* DMA Engine 1 Current Count Register */
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#define CS4281_DBA1 0x128 /* DMA Engine 1 Base Address Register */
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#define CS4281_DBC1 0x12C /* DMA Engine 1 Base Count Register */
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#define CS4281_DCA2 0x130 /* DMA Engine 2 Current Address Register */
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#define CS4281_DCC2 0x134 /* DMA Engine 2 Current Count Register */
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#define CS4281_DBA2 0x138 /* DMA Engine 2 Base Address Register */
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#define CS4281_DBC2 0x13C /* DMA Engine 2 Base Count Register */
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#define CS4281_DCA3 0x140 /* DMA Engine 3 Current Address Register */
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#define CS4281_DCC3 0x144 /* DMA Engine 3 Current Count Register */
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#define CS4281_DBA3 0x148 /* DMA Engine 3 Base Address Register */
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#define CS4281_DBC3 0x14C /* DMA Engine 3 Base Count Register */
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#define CS4281_DMR0 0x150 /* DMA Engine 0 Mode Register */
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#define CS4281_DCR0 0x154 /* DMA Engine 0 Command Register */
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#define CS4281_DMR1 0x158 /* DMA Engine 1 Mode Register */
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#define CS4281_DCR1 0x15C /* DMA Engine 1 Command Register */
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#define CS4281_DMR2 0x160 /* DMA Engine 2 Mode Register */
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#define CS4281_DCR2 0x164 /* DMA Engine 2 Command Register */
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#define CS4281_DMR3 0x168 /* DMA Engine 3 Mode Register */
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#define CS4281_DCR3 0x16C /* DMA Engine 3 Command Register */
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/* DMRn common bit description*/
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#define DMRn_DMA 0x20000000
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#define DMRn_POLL 0x10000000
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#define DMRn_TBC 0x02000000
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#define DMRn_CBC 0x01000000
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#define DMRn_SWAPC 0x00400000
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#define DMRn_SIZE20 0x00100000
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#define DMRn_USIGN 0x00080000
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#define DMRn_BEND 0x00040000
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#define DMRn_MONO 0x00020000
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#define DMRn_SIZE8 0x00010000
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#define DMRn_FMTMSK ( DMRn_SWAPC | DMRn_SIZE20 | DMRn_USIGN | DMRn_BEND | DMRn_MONO | DMRn_SIZE8 )
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#define DMRn_TYPE1 0x00000080
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#define DMRn_TYPE0 0x00000040
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#define DMRn_DEC 0x00000020
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#define DMRn_AUTO 0x00000010
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#define DMRn_TR_MASK 0x0000000c
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#define DMRn_TR_READ 0x00000008
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#define DMRn_TR_WRITE 0x00000004
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/* DCRn common bit description*/
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#define DCRn_HTCIE 0x00020000 /* Half Terminal Count Interrupt Enable */
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#define DCRn_TCIE 0x00010000 /* Terminal Count Interrupt Enable */
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#define DCRn_MSK 0x00000001
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#define CS4281_FCR0 0x180 /* FIFO Control Register 0 */
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#define CS4281_FCR1 0x184 /* FIFO Control Register 1 */
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#define CS4281_FCR2 0x188 /* FIFO Control Register 2 */
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#define CS4281_FCR3 0x18C /* FIFO Control Register 3 */
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#define FCRn_FEN 0x80000000
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#define FCRn_DACZ 0x40000000
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#define FCRn_PSH 0x20000000
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#define CS4281_FPDR0 0x190 /* FIFO Polled Data Register 0 */
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#define CS4281_FPDR1 0x194 /* FIFO Polled Data Register 1 */
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#define CS4281_FPDR2 0x198 /* FIFO Polled Data Register 2 */
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#define CS4281_FPDR3 0x19C /* FIFO Polled Data Register 3 */
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#define CS4281_FCHS 0x20C /* FIFO Channel Status */
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#define CS4281_FSIC0 0x210 /* FIFO Status and Interrupt Control Register 0 */
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#define CS4281_FSIC1 0x214 /* FIFO Status and Interrupt Control Register 1 */
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#define CS4281_FSIC2 0x218 /* FIFO Status and Interrupt Control Register 2 */
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#define CS4281_FSIC3 0x21C /* FIFO Status and Interrupt Control Register 3 */
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#if 0
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300h - 340h /* PCI Configuration Space Echo, offsets 00h - 42h, RO */
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#endif
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#define CS4281_PCICFG00 0x300
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#define CS4281_PCICFG04 0x304
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#define CS4281_PMCS 0x344 /* Power Management Control/Status */
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#define CS4281_CWPR 0x3E0 /* Configuration Write Protect Register */
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#define CS4281_EPPMC 0x3E4 /* Extended PCI Power Management Control */
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#define EPPMC_FPDN (0x1 << 14)
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#define CS4281_GPIOR 0x3E8 /* GPIO Pin Interface Register */
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#define CS4281_SPMC 0x3EC /* Serial Port Power Management Control (& ASDIN2 enable) */
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#define SPMC_RSTN 0x00000001
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#define SPMC_ASYN 0x00000002
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#define SPMC_WUP1 0x00000004
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#define SPMC_WUP2 0x00000008
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#define SPMC_ASDO 0x00000080
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#define SPMC_ASDI2E 0x00000100
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#define SPMC_EESPD 0x00000200
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#define SPMC_GISPEN 0x00000400
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#define SPMC_GIPPEN 0x00008000
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#define CS4281_CFLR 0x3F0 /* Configuration Load Register (EEPROM or BIOS) */
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#define CS4281_IISR 0x3F4 /* ISA Interrupt Select Register */
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#define CS4281_TMS 0x3F8 /* Test Register - Reserved */
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#define CS4281_SSVID 0x3FC /* Subsystem ID register (read-only version at 32Ch) */
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#define CS4281_CLKCR1 0x400 /* Clock Control Register 1 */
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#define CLKCR1_DLLSS0 0x00000004
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#define CLKCR1_DLLSS1 0x00000008
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#define CLKCR1_DLLP 0x00000010
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#define CLKCR1_SWCE 0x00000020
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#define CLKCR1_DLLOS 0x00000040
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#define CLKCR1_CKRA 0x00010000
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#define CLKCR1_CKRN 0x00020000
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#define CLKCR1_DLLRDY 0x01000000
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#define CLKCR1_CLKON 0x02000000
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#define CS4281_FRR 0x410 /* Feature Reporting Register */
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#define CS4281_SLT12O 0x41C /* Slot 12 GPIO Output Register for AC Link */
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#define CS4281_SERMC 0x420 /* Serial Port Master Control Register */
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#define SERMC_MSPE 0x00000001
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#define SERMC_PTCMASK 0x0000000E
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#define SERMC_PTCAC97 0x00000002
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#define SERMC_PLB 0x00000100
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#define SERMC_PXLB 0x00000200
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#define SERMC_TCID0 0x00010000
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#define SERMC_TICD1 0x00020000
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#define SERMC_LOVF 0x00080000
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#define SERMC_SLB 0x00100000
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#define SERMC_SXLB 0x00200000
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#define SERMC_ODSEN1 0x01000000
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#define SERMC_ODSEN2 0x02000000
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#define SERMC_FCRN 0x08000000
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#define CS4281_SERC1 0x428 /* Serial Port Configuration Register 1 - RO */
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#define CS4281_SERC2 0x42C /* Serial Port Configuration Register 2 - RO */
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#define CS4281_SLT12M 0x45C /* Slot 12 Monitor Register for Primary AC Link */
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/*
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* AC97 Registers are moved to cs428xreg.h since
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* they are common for CS4280 and CS4281
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*/
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#define CS4281_JSPT 0x480 /* Joystick Poll/Trigger Register */
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#define CS4281_JSCTL 0x484 /* Joystick Control Register */
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#define CS4281_MIDCR 0x490 /* MIDI Control Register */
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#define CS4281_MIDCMD 0x494 /* MIDI Command Register - WO */
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#define CS4281_MIDSR 0x494 /* MIDI Status Register - RO */
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#define CS4281_MIDWP 0x498 /* MIDI Write Port */
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#define CS4281_MIDRP 0x49C /* MIDI Read Port - RO */
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#define CS4281_AODSD1 0x4A8 /* AC `97 On-Demand Slot Disable for primary link - RO */
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#define CS4281_AODSD2 0x4AC /* AC `97 On-Demand Slot Disable for secondary link - RO */
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#define CS4281_CFGI 0x4B0 /* Configuration Interface Register (EEPROM interface) */
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#define CS4281_SLT12M2 0x4DC /* Slot 12 Monitor Register 2 for Secondary AC Link */
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#define CS4281_ACSTS2 0x4E4 /* AC 97 Status Register 2 */
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#define ACSTS2_CRDY2 0x00000001
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#define ACSTS2_BSYS2 0x00000002
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#define CS4281_ACISV2 0x4F4 /* AC 97 Input Slot Valid Register 2 */
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#define CS4281_ACSAD2 0x4F8 /* AC 97 Status Address Register 2 */
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#define CS4281_ACSDA2 0x4FC /* AC 97 Status Data Register 2 */
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#define CS4281_FMSR 0x730 /* FM Synthesis Status Register - RO */
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#define CS4281_B0AP 0x730 /* FM Bank 0 Address Port - WO */
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#define CS4281_FMDP 0x734 /* FM Data Port */
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#define CS4281_B1AP 0x738 /* FM Bank 1 Address Port */
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#define CS4281_B1DP 0x73C /* FM Bank 1 Data Port */
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#define CS4281_SSPM 0x740 /* Sound System Power Management */
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#define SSPM_ALL 0x0000007E
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#define SSPM_MIXEN 0x00000040 /* p167 */
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#define SSPM_CSRCEN 0x00000020
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#define SSPM_PSRCEN 0x00000010
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#define SSPM_JSEN 0x00000008
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#define SSPM_ACLEN 0x00000004
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#define SSPM_FMEN 0x00000002
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#define CS4281_DACSR 0x744 /* DAC Sample Rate - Playback SRC */
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#define CS4281_ADCSR 0x748 /* ADC Sample Rate - Capture SRC */
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#define CS4281_SSCR 0x74C /* Sound System Control Register */
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#define SSCR_HVS1 0x00800000 /* Hardware Volume step by 1 */
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#define SSCR_MVCS 0x00080000 /* Master Volume Codec Select */
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#define SSCR_MVLD 0x00040000 /* Master Volume Line Out Disable */
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#define SSCR_MVAD 0x00020000 /* Master Volume Alternate Out Disable */
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#define SSCR_MVMD 0x00010000 /* Master Volume Mono Out Disable */
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#define SSCR_XLPSRC 0x00000100 /* External SRC loopback mode */
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#define SSCR_LPSRC 0x00000080 /* SRC loopback mode */
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#define SSCR_CDTX 0x00000020 /* CD Transfer Data */
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#define SSCR_HVC 0x00000008 /* Hardware Volume Control Enable */
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#define CS4281_FMLVC 0x754 /* FM Synthesis Left Volume Control */
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#define CS4281_FMRVC 0x758 /* FM Synthesis Right Volume Control */
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#define CS4281_SRCSA 0x75C /* SRC Slot Assignments */
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#define CS4281_PPLVC 0x760 /* PCM Playback Left Volume Control */
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#define CS4281_PPRVC 0x764 /* PCM Playback Right Volume Control */
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/* Base Address 1 Direct Memory Map */
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#if 0
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0000h - 03FFh FIFO RAM Audio Sample RAM Memory Block - FIFOs
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Logical Size: 256 x 32 bits (1 kbytes stereo double words)
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0400h - D51Fh Reserved Reserved internal memory
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D600h - FFFFh Reserved Reserved for future use
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#endif
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/* for AC97_REG_POWER */
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#define CS4281_POWER_DOWN_ALL 0x7f0f
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