103 lines
4.5 KiB
C
103 lines
4.5 KiB
C
/* $NetBSD: motoi2creg.h,v 1.3 2014/10/07 21:32:10 matt Exp $ */
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/*-
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* Copyright (c) 2007, 2010 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_I2C_MOTOI2CREG_H_
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#define _DEV_I2C_MOTOI2CREG_H_
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/*
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* This I2C controller is a common design used on many Motorola/Freescale
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* chip like the i.MX/MC9328, MPC8548, etc. Different names in bit field
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* definition and not suffered from document error.
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*/
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#define I2CADR 0x0000 /* my own I2C addr to respond for an external master */
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#define I2CFDR 0x0004 /* frequency devider */
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#define I2CCR 0x0008 /* control */
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#define CR_MEN 0x80 /* enable this HW */
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#define CR_MIEN 0x40 /* enable interrupt */
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#define CR_MSTA 0x20 /* 0->1 activates START, 1->0 makes STOP condition */
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#define CR_MTX 0x10 /* 1 for Tx, 0 for Rx */
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#define CR_TXAK 0x08 /* 1 makes no acknowledge when Rx */
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#define CR_RSTA 0x04 /* generate repeated START condition */
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#define I2CSR 0x000c /* status */
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#define SR_MCF 0x80 /* 0 means transfer in progress, 1 when completed */
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#define SR_MAAS 0x40 /* 1 means addressed as slave */
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#define SR_MBB 0x20 /* 1 before STOP condition is detected */
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#define SR_MAL 0x10 /* arbitration was lost */
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#define SR_MIF 0x02 /* indicates data transter completion */
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#define SR_RXAK 0x01 /* 1 to indicate receive has completed */
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#define I2CDR 0x0010 /* data */
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#define I2CDFSRR 0x0014 /* digital filter sampling rate register */
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/*
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* The equation to calculate the divider frequency (from AN2919) is:
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*
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* Frequency divider = B * (A + (floor(3 * C / B) * 2))
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*
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* where (in little endian bit order, msb to lsb) FDR is split into 2 3-bit
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* fields: fA contains bits 5,1,0 and fB contains bits 4,3,2.
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*
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* A is used as an index into { 9, 10, 12, 15, 5, 6, 7, 8 } though
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* on faster machines these are doubled to { 18, 20, 24, 50, 10, 12, 14, 16 }.
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* B is either 2**(b + 1) or 2**(b + 4).
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*
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* C is the sampling rate, which may be settable via I2CDFSRR register though
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* not all implementations have it. Regardless, we just leave it at its
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* default setting (16). So floor(3 * C / B) * 2 becomes a precomputable
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* quantity. Once we know its value for fB=0, we can simply shift it right
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* as fB increases since B is a power-of-2.
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*/
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#define FDR_A(n) (((n) & 0x20) >> 3) | ((n) & 3))
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#define FDR_B(n) (((n) & 0x1c) >> 2)
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#define MOTOI2C_GROUP_A_VALUES 0x8765fca9U
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#define MOTOI2C_A(a) ((MOTOI2C_GROUP_A_VALUE >> (4*(a))) & 0xf)
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#define MOTOI2C_B(b) (1 + (b))
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#define MOTOI2C_DIV(name, fdr) \
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((name##_A(FDR_A(fdr)) + named##_C(FDR_B(fdr))) << name##_B(FDR_B(fdr)))
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#define IMX31_A(fdr_a) MOTOI2C_A(fdr_a)
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#define IMX31_B(fdr_b) MOTOI2C_B(fdr_b)
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#define IMX31_C(fdr_b) (6 >> (fdr_b))
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#define IMX31_DIV(fdr) MOTOI2C_DIV(IMX31, fdr)
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#define MCF52259_A(fdr_a) MOTOI2C_A(fdr_a)
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#define MCF52259_B(fdr_b) MOTOI2C_B(fdr_b)
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#define MCF52259_C(fdr_b) (5 >> (fdr_b))
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#define MCF52259_DIV(fdr) MOTOI2C_DIV(MCF52259, fdr)
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#define MPC85xx_A(fdr_a) (MOTOI2C_A(fdr_a) << 1)
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#define MPC85xx_B(fdr_b) (4 + (fdr_b))
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#define MPC85xx_C(fdr_b) ((6 >> (fdr_b)) & ~1)
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#define MPC85xx_DIV(fdr) MOTOI2C_DIV(MPC85xx, fdr)
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#endif /* !_DEV_I2C_MOTOI2CREG_H_ */
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