184 lines
7.4 KiB
C
184 lines
7.4 KiB
C
/*-
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* Copyright (c) 2002-2006 Sam Leffler, Errno Consulting, Atheros
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* Communications, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms are permitted
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* provided that the following conditions are met:
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* 1. The materials contained herein are unmodified and are used
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* unmodified.
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* 2. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following NO
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* ''WARRANTY'' disclaimer below (''Disclaimer''), without
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* modification.
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* 3. Redistributions in binary form must reproduce at minimum a
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* disclaimer similar to the Disclaimer below and any redistribution
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* must be conditioned upon including a substantially similar
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* Disclaimer requirement for further binary redistribution.
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* 4. Neither the names of the above-listed copyright holders nor the
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* names of any contributors may be used to endorse or promote
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* product derived from this software without specific prior written
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* permission.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ''AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT,
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* MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE
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* FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGES.
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*
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* $Id: ah_desc.h,v 1.2 2006/06/05 05:14:38 gdamore Exp $
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*/
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#ifndef _DEV_ATH_DESC_H
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#define _DEV_ATH_DESC_H
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/*
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* Transmit descriptor status. This structure is filled
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* in only after the tx descriptor process method finds a
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* ``done'' descriptor; at which point it returns something
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* other than HAL_EINPROGRESS.
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*
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* Note that ts_antenna may not be valid for all h/w. It
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* should be used only if non-zero.
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*/
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struct ath_tx_status {
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u_int16_t ts_seqnum; /* h/w assigned sequence number */
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u_int16_t ts_tstamp; /* h/w assigned timestamp */
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u_int8_t ts_status; /* frame status, 0 => xmit ok */
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u_int8_t ts_rate; /* h/w transmit rate index */
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#define HAL_TXSTAT_ALTRATE 0x80 /* alternate xmit rate used */
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int8_t ts_rssi; /* tx ack RSSI */
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u_int8_t ts_shortretry; /* # short retries */
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u_int8_t ts_longretry; /* # long retries */
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u_int8_t ts_virtcol; /* virtual collision count */
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u_int8_t ts_antenna; /* antenna information */
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};
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#define HAL_TXERR_XRETRY 0x01 /* excessive retries */
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#define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */
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#define HAL_TXERR_FIFO 0x04 /* fifo underrun */
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/*
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* Receive descriptor status. This structure is filled
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* in only after the rx descriptor process method finds a
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* ``done'' descriptor; at which point it returns something
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* other than HAL_EINPROGRESS.
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*
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* If rx_status is zero, then the frame was received ok;
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* otherwise the error information is indicated and rs_phyerr
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* contains a phy error code if HAL_RXERR_PHY is set. In general
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* the frame contents is undefined when an error occurred thought
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* for some errors (e.g. a decryption error), it may be meaningful.
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*
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* Note that the receive timestamp is expanded using the TSF to
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* 15 bits (regardless of what the h/w provides directly).
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*
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* rx_rssi is in units of dbm above the noise floor. This value
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* is measured during the preamble and PLCP; i.e. with the initial
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* 4us of detection. The noise floor is typically a consistent
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* -96dBm absolute power in a 20MHz channel.
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*/
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struct ath_rx_status {
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u_int16_t rs_datalen; /* rx frame length */
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u_int16_t rs_tstamp; /* h/w assigned timestamp */
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u_int8_t rs_status; /* rx status, 0 => recv ok */
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u_int8_t rs_phyerr; /* phy error code */
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int8_t rs_rssi; /* rx frame RSSI */
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u_int8_t rs_keyix; /* key cache index */
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u_int8_t rs_rate; /* h/w receive rate index */
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u_int8_t rs_antenna; /* antenna information */
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u_int8_t rs_more; /* more descriptors follow */
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};
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#define HAL_RXERR_CRC 0x01 /* CRC error on frame */
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#define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */
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#define HAL_RXERR_FIFO 0x04 /* fifo overrun */
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#define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
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#define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */
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enum {
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HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */
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HAL_PHYERR_TIMING = 1, /* Timing error */
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HAL_PHYERR_PARITY = 2, /* Illegal parity */
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HAL_PHYERR_RATE = 3, /* Illegal rate */
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HAL_PHYERR_LENGTH = 4, /* Illegal length */
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HAL_PHYERR_RADAR = 5, /* Radar detect */
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HAL_PHYERR_SERVICE = 6, /* Illegal service */
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HAL_PHYERR_TOR = 7, /* Transmit override receive */
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/* NB: these are specific to the 5212 */
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HAL_PHYERR_OFDM_TIMING = 17, /* */
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HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */
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HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */
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HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */
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HAL_PHYERR_OFDM_POWER_DROP = 21, /* */
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HAL_PHYERR_OFDM_SERVICE = 22, /* */
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HAL_PHYERR_OFDM_RESTART = 23, /* */
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HAL_PHYERR_CCK_TIMING = 25, /* */
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HAL_PHYERR_CCK_HEADER_CRC = 26, /* */
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HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */
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HAL_PHYERR_CCK_SERVICE = 30, /* */
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HAL_PHYERR_CCK_RESTART = 31, /* */
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};
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/* value found in rs_keyix to mark invalid entries */
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#define HAL_RXKEYIX_INVALID ((u_int8_t) -1)
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/* value used to specify no encryption key for xmit */
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#define HAL_TXKEYIX_INVALID ((u_int) -1)
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/* XXX rs_antenna definitions */
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/*
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* Definitions for the software frame/packet descriptors used by
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* the Atheros HAL. This definition obscures hardware-specific
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* details from the driver. Drivers are expected to fillin the
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* portions of a descriptor that are not opaque then use HAL calls
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* to complete the work. Status for completed frames is returned
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* in a device-independent format.
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*/
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struct ath_desc {
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/*
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* The following definitions are passed directly
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* the hardware and managed by the HAL. Drivers
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* should not touch those elements marked opaque.
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*/
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u_int32_t ds_link; /* phys address of next descriptor */
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u_int32_t ds_data; /* phys address of data buffer */
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u_int32_t ds_ctl0; /* opaque DMA control 0 */
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u_int32_t ds_ctl1; /* opaque DMA control 1 */
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u_int32_t ds_hw[4]; /* opaque h/w region */
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/*
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* The remaining definitions are managed by software;
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* these are valid only after the rx/tx process descriptor
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* methods return a non-EINPROGRESS code.
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*/
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union {
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struct ath_tx_status tx;/* xmit status */
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struct ath_rx_status rx;/* recv status */
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} ds_us;
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void *ds_vdata; /* virtual addr of data buffer */
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} __packed;
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#define ds_txstat ds_us.tx
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#define ds_rxstat ds_us.rx
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/* flags passed to tx descriptor setup methods */
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#define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */
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#define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */
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#define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */
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#define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */
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#define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */
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#define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */
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/* NB: this only affects frame, not any RTS/CTS */
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#define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */
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/* flags passed to rx descriptor setup methods */
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#define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */
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#endif /* _DEV_ATH_AR521XDMA_H */
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