90 lines
3.2 KiB
C
90 lines
3.2 KiB
C
/* $NetBSD: pciide_cmd_reg.h,v 1.5 1999/08/29 17:20:10 bouyer Exp $ */
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/*
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* Copyright (c) 1998 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Registers definitions for CMD Technologies's PCI 064x IDE controllers.
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* Available from http://www.cmd.com/
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*/
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/* Configuration (RO) */
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#define CMD_CONF 0x50
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#define CMD_CONF_REV_MASK 0x03
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#define CMD_CONF_DRV0_INTR 0x04
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#define CMD_CONF_DEVID 0x18
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#define CMD_CONF_VESAPRT 0x20
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#define CMD_CONF_DSA1 0x40
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#define CMD_CONF_DSA0 0x80
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/* Control register (RW) */
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#define CMD_CTRL 0x51
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#define CMD_CTRL_HR_FIFO 0x01
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#define CMD_CTRL_HW_FIFO 0x02
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#define CMD_CTRL_DEVSEL 0x04
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#define CMD_CTRL_2PORT 0x08
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#define CMD_CTRL_PAR 0x10
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#define CMD_CTRL_HW_HLD 0x20
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#define CMD_CTRL_DRV0_RAHEAD 0x40
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#define CMD_CTRL_DRV1_RAHEAD 0x80
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/*
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* data read/write timing registers . 0640 uses the same for drive 0 and 1
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* on the secondary channel
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*/
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#define CMD_DATA_TIM(chan, drive) \
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(((chan) == 0) ? \
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((drive) == 0) ? 0x54: 0x56 \
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: \
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((drive) == 0) ? 0x58 : 0x5b)
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/* secondary channel status and addr timings */
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#define CMD_ARTTIM23 0x57
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#define CMD_ARTTIM23_IRQ 0x10
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#define CMD_ARTTIM23_RHAEAD(d) ((0x4) << (d))
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/* DMA master read mode select */
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#define CMD_DMA_MODE 0x71
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#define CMD_DMA 0x00
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#define CMD_DMA_MULTIPLE 0x01
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#define CMD_DMA_LINE 0x10
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/*
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* timings values for the 0643 and 0x646
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* for all dma_mode we have to have
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* DMA_timings(dma_mode) >= PIO_timings(dma_mode + 2)
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*/
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static int8_t cmd0643_6_data_tim_pio[] = {0xA9, 0x57, 0x44, 0x32, 0x3F};
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static int8_t cmd0643_6_data_tim_dma[] = {0x87, 0x32, 0x3F};
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